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GPS Signal Synchronization Algorithms Specific Extension of ARCA3 Instruction-Set

Author: LiuChangSong
Tutor: LaiFengChang
School: Harbin Institute of Technology
Course: Microelectronics and Solid State Electronics
Keywords: GPS Software Receiver Signal synchronization ASIP Hardware and software co-design ARCA3
CLC: TN967.1
Type: Master's thesis
Year: 2009
Downloads: 16
Quote: 1
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Abstract


Signal synchronization unit is a GPS receiver of the main arithmetic unit, complete the main functions of the C / A code phase and Doppler frequency shift to generate a local signal synchronized with the received signal , thereby accurately estimate the carrier frequency and C / A The code is stripped from the received signal to extract the navigation message for subsequent unit for positioning solver . Signal synchronization including the capture and tracking of a two-stage , its core operation unit is a GPS receiver main the computing bottleneck , has been plagued embedded real-time software receiver design is the key problem . The design of the GPS signal synchronization capture and tracking algorithm studies optimization and ARCA3 embedded microprocessor soft core , expansion -oriented capture and trace operation dedicated instruction , explore ASIP - based GPS signal synchronization the algorithm embedded real-time solutions. Based on hardware and software co-design approach , the ASIP design is divided into two system-level and RTL design phase . In system-level design stage , fast instruction set design space exploration , the establishment of an instruction set simulator , and assembler software tools for system-level hardware and software co-simulation platform design . Adding the corresponding functional unit and the control logic in the RTL-level design stage , through the pipeline structure to modify ARCA3 soft core of dedicated instruction be achieved ; using a cycle-accurate simulation platform for a more accurate assessment of the performance of the ASIP hardware and software co-simulation , and ASIP RTL level HDL code optimization , a comprehensive assessment system parameters according to area , timing , power consumption , FPGA test platform the ASIP on actual function of . The simulation results show that , compared with ARCA3 , ASIP run correlator efficiency greatly improved , conducive to real-time implementation of the GPS signal synchronization algorithms and embedded software GPS receiver .

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Radio navigation > Navigation systems of the various institutional > Satellite navigation system
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