|
With the development of mobile communication , multimedia technologies and the Internet , the demand for image , brought difficulties to the limited transmission bandwidth and storage space , so it is necessary for processing and compression of image data . JPEG2000 is a new generation of international still image compression standard , it not only has a high compression performance , but also provide a lot of good features , and therefore has a broad application prospects in many areas of the Internet , remote sensing , and print . The papers in -depth study of the the standard JPEG2000 core coding algorithm based on a high-speed , real-time JPEG2000 encoding system FPGA implementations . First, the bit plane coding algorithm EBCOT Tier-1 encoder , and analysis of the existing types of hardware acceleration , as a basis , the proposed bit-plane -based the group hop and code block parallel encoder structure, which greatly reduces the data reading and processing time ; Secondly, in the hardware implementation of the arithmetic coder , in order to match the bit plane coding the high processing ability , the use of multi - MQ coder parallel architectures , and presents a the four MQ encoder pipeline structure , greatly improve the data throughput capacity of MQ encoder ; again, EBCOT Tier-2 encoder rate control algorithm , suitable for high-speed real-time compression hardware to achieve rate control programs - the progressive channel truncate multi- encoder parallel algorithm greatly improve the coding efficiency , saving storage space : Finally, the use of Xilinx's XC2V3000-4 FPGA chip implementation of the JPEG2000 encoding system , the real-time compression , through simulation and testing system function properly , and be able to handle 240 512 × 512 gray-scale images per second .
|