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Multi-chip Digital Test Based on the BSC of FPGA

Author: GongYinShui
Tutor: JiangXiaoBo；LiHuiYun
School: South China University of Technology
Course: IC Engineering
Keywords: FPGA BSC boundary scan daisy chain interconnection Boundary-scan test
CLC: TN407
Type: Master's thesis
Year: 2011
Downloads: 82
Quote: 0
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Abstract


With the increasing scale of integrated circuits and multi-chip system package ,especially the rapid development of the systems on a circuit (SOC),the number of test pins become small, so that the chips are not easy to test, also with the single-chip functional test and interconnections of the multi-chip system. The design for test becomes very import because that the traditional bed of nails test cannot achieve high test coverage.This paper studies the design for test, the boundary-scan principle and the daisy chains. We proposed the daisy chain expansion to test DUT based on the BSCs of FPGA for the test of the multi-chip package system. We build the hardware and software platforms to complete the test results, and measure the controllability and observability of chips with SCOAP testability algorithm in theory. This paper reviews the design for test, boundary-scan principle, boundary scan architecture and the developments of chip test. The boundary-scan test is the best in the board-level tests and the programmable logic device FPGA (Field-Programmable Gate Array) has a large number of boundary-scan cells. Based on the boundary-scan principle, we propose the multi-chip digital test method based on the BSC of FPGA because of the problem of no boundary scan test structure in one (or more) chip in the multi-chip system, so we can test all chips fully automated to improve test efficiency and build the hardware and software platform to complete the multi-chip package system test results. At last, we also summarize and prospect the shortcomings of the proposed method.We propose a new method that the non-test part of a SIP chip can be easily tested with the boundary-scan test utilizing the boundary scan chain of the FPGA. The problem of no boundary scan test structure in one (or more) chip in a system-in-package (SIP) can be solved by connecting the interconnection(s) to be tested to the FPGA to form an enlarged boundary scan daisy chain.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Microelectronics, integrated circuit (IC) > General issues > Testing and inspection
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