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Design of LCD Driver Interface Based on MIPI Specifications

Author: SuXiaoFeng
Tutor: CaiMin；LiangZuoShu
School: South China University of Technology
Course: IC Engineering
Keywords: MIPI Verilog HDL LCD Driver Interface
CLC: TN873.93
Type: Master's thesis
Year: 2011
Downloads: 94
Quote: 0
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Abstract


With the development of smart mobile devices, mobile devices screen size and the mobile processor frequency increases, the demand for data traffic rising, while maintaining high performance and low power requirements, the traditional display interface has been gradually revealed the disadvantages. So the display interface based on MIPI came into being, MIPI-DSI is a high-speed serial interface with low-power, strong anti-interference ability.The paper is based on the MIPI specification that can be applied to HVGA LCD driver interface. This paper start with the background and research topics, have a brief description of MIPI specifications, than given the overall system architecture, and the Physical Layer, Lane Management, Low-level protocol, Application layer for detailed circuit analysis and design to achieve.Verilog HDL is used for RTL-level description of all circuits modules.At last, establishment of the simulation platform with the VCS simulation, write a comprehensive constraint files with DC, and gives the simulation waveforms with the synthesis results.The innovation of this paper are to achieve optimal system architecture,streamlined system of non-essential functions, access control circuit using three-state machine of one-hot coding. In the system structure, the Physical Layer composed of a single high-speed logic part of the functional modules, easy to follow comprehensive optimization and timing analysis; in thestreamlining of the system functionality, the interface supports clock lane and a data lane (up to 4 lanes), removed 8b9b encoding and chip test modulefunctions and so on,This can greatly reduce the system power consumption and circuit area; the clock lane and data lane in the state transitions of the state machine with three-stage one-hot code coding, simplifies the decoding logic,reducing the probability of glitch produced.This can enhance the stability of the circuit state transition; Used parameters of the configuration options for part of the state in the design and function of the time in order to improve application flexibilityAfter a comprehensive analysis on the simulation results and synthesis report, the design achieves the technical requirements. Process library is Maxchip 0.11μm, the power consumption is 3.7971mW, the area of circuit is 59056.0812μm2, with the highest working frequency of 500MHZ.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Radio equipment,telecommunications equipment > Terminal equipment > Display device,the display > LCD monitors
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