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Encryption Design and Implementation for Programmable Logic Device

Author: WangSongMing
Tutor: YuGang；HuZhiYong
School: Harbin Institute of Technology
Course: Mechanical and Electronic Engineering
Keywords: Programmable logic devices Random Number Generator Encryption Smart Card
CLC: TP309.7
Type: Master's thesis
Year: 2008
Downloads: 34
Quote: 0
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Abstract

Programmable logic devices not only inherited the large-scale application specific integrated circuit, high integration, high reliability advantages, but also overcome the ASIC design cycle, large investment, the shortcomings of poor flexibility, and gradually become complex digital hardware circuit design ideal choice. The most frightening thing is put into the design work for several months, worked so hard to design results theft. Therefore, the programmable logic device security issues more and more people's attention. SRAM (static random access memory) process programmable logic device, the requirements of each power-on, the reconfigurable programmable logic device, which makes the data bit stream can be configured by monitoring cloning design. Flash / Anti-Fuse process programmable logic device, by releasing the security bit on the chip, the chip allows readback operation, the device in the circuit so the thief can be obtained. In order to protect the intellectual property rights, and some programmable logic devices are now able to bit stream encryption. The programmable logic device configuration bitstream, however, do not have the embedded bitstream encryption means to encrypt the key for programming the programmable logic device need to increase steps in the production process, thus increasing the cost. For high-volume applications, encrypted storage card cost will be higher. Programmable logic devices confidentiality depth analysis of the proposed use encrypted memory card safety certification programmable logic device encryption design, to improve the design of existing programmable logic device encryption, simplify the circuit on the basis of, reduce costs, and strengthen security. Calculation results match the programmable logic device and the encryption algorithm in the memory card, this option is disabled before the design of programmable logic devices, and therefore, even if access to the configuration data bit stream, the design is safe. Random number generator has been widely applied in many aspects of the encryption key generation, encryption, storage, a lot of the security of the encryption system is directly dependent on the unpredictability of the key as well as non-correlation. Although the random number generator has a wide range of applications, but rarely generate true random number random number generator. Which IC (Integrated Circuit) technology compatible with the random number generator in three ways: amplifier circuit noise, oscillation sampling and chaotic circuit. This paper presents a new implementation of the random number generator based on FPGA (Filed Programmable Gate Array) delay uncertainty, easier to use FPGA design and implementation. The proposed program by the U.S. Department of Commerce National Institute of Standards and Technology Association released NIST FIPS 140-1 randomness statistical tests. The statistical tests show that this paper a kind of good random number generator random number generator has good statistical properties, which has good value in use. The prototype of this design is implemented in Altera Cyclone II series EP2C8Q208C8 device and verified, a clock frequency of 40 MHz, the time-consuming encryption and authentication of approximately 30ms, occupy a total of 1139 LE (Altera FPGA logic unit), 732 register (edge ??triggering ) and three pin.

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CLC: > Industrial Technology > Automation technology,computer technology > Computing technology,computer technology > General issues > Security and confidentiality > Encryption and decryption
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