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Design and Implementation of Intrusion Prevention System Based on Network Multi-core Processor

Author: BianRuiFeng
Tutor: WangQuan；ChenBin
School: Xi'an University of Electronic Science and Technology
Course: Software Engineering
Keywords: Network Multi-core Processor Inter-core Communication Bootloader NIPS Performance Evaluation
CLC: TN915.08
Type: Master's thesis
Year: 2009
Downloads: 33
Quote: 3
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Abstract


The development of high-speed communications network requires the support of high-performance network equipments and at the same time high-performance network equipments demand high-performance processors. Multi-core architecture by increasing the number of physical computer processors makes the program run in parallel which can be used as an effective way to improve the performance of the processor.The study composes the trend of the CPU which develops from a single core to multi-core and the architecture of MIPS; analyzes the MIPS 64bit multi-core OCTEON CPU hardware structure, the processing flow of packets and parallel program technology. According to OCTEON CPU it summarizes the loading and the process of embedded software, analyses the software design model and inter-core communication technology. Based on the open-source software snort, this thesis utilizes multi-core architecture and integrated hardware accelerating units to produce an effective NIPS and analyses the program optimization technology in connection with hardware. Finally, the thesis also tests and analyses the network packet processing capabilities and performance of the NIPS.According to the test results of NIPS, it can be seen that multi-core architecture greatly enhances network packet processing capabilities and performance of NIPS which has reached the goal as expected.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Communicate > Communication network > General issues > Network Security
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