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Power gating analysis of key technologies and circuit design

Author: ZhangLiDi
Tutor: XiaoLiYi
School: Harbin Institute of Technology
Course: Microelectronics and Solid State Electronics
Keywords: Power gating Gated transistor insertion algorithm Reflecting Data Hold
CLC: TN432
Type: Master's thesis
Year: 2008
Downloads: 13
Quote: 0
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Abstract


As transistors continue to shrink the size of the manufacturing process , the threshold voltage is reduced , resulting in exponential growth static power consumption , reduce static power CMOS integrated circuit design has become an increasingly important goal. This reduces static power for power gating technique studied based on the maximum gate current clustering algorithm based on the time gating signal control method designed to reduce reflection of the new and improved stepped voltage generating circuit delay control structure , data held in the data holding structure clamped and data holding register , suppressing gate leakage current input control circuit and the dual power source structure . This paper analyzes the power gating of key technologies. Power gating techniques for static power reduction effect is very obvious, but there are still some problems to be solved . In the power gating techniques to realize , the paper used for the whole circuit insertion door control switch clustering algorithms , the static power consumption of the circuit is about 90% , the performance loss is less than 5%. Time-based control principle , the design of the gate control signal control circuit , it can monitor the state of the circuit module to generate the gate control input signal , activation time of only 2.3% of the clock period . Since the power gating techniques may cause reflected , data loss and the gate leakage current and other effects , the paper design of new and improved stepped voltage generating circuit control circuit to reduce the delay to reflect the two programs have achieved good results . By inserting the clamp transistor way to achieve data retention, and designed with data hold function registers can be power gating technique instead of ordinary registers. Because the gate leakage current on the circuit of the original input , so this paper uses the input control circuit for suppressing gate leakage current , and designed a dual power structure, while suppressing the subthreshold current and gate leakage current. Finally, the above technique applied to the circuit design. Based on SMIC SMIC CMOS 90nm process model, 1.0V supply voltage conditions, the use of HSPICE simulation tools to complete the various parts of the circuit simulation results show that the static power consumption reduced by 90 %, the performance loss is less than 5% , only area increased more than 100% .

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Microelectronics, integrated circuit (IC) > Semiconductor integrated circuits ( solid state circuits ) > Field-effect type
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