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With the development of society, people need volume smaller, lower power consumption, lower cost IC (Integrated Circuit, integrated circuit). It is this strong demand has greatly promoted the development of the semiconductor IC packaging technology. The the traditional IC two-dimensional package, the wire bonding of each chip is connected. Accordingly, the information transmission through the additional channel, transmission distance, the signal is delayed by a certain extent. The traditional 3D IC package are chip stacked vertically arranged, but still the wire bonding method to connect the individual chips, the same lack of information transmission path longer exists. Compared to traditional two-dimensional and three-dimensional IC package, three-dimensional package using TSV technology, longer wire bonding, effectively reduced the information transmission path, speed chip-to-chip connection between the chip and the outside The data transmission speed, effectively reducing the delay and loss of information in the transmission process. In the packaging area of ??the same case, TSV technology can make packaging products structure has a higher density, more features, better performance, cheaper cost. In order to achieve the IC device TSV (Through Silicon Via penetrate silicon vias) wafer-level packaging, you need to complete the development of several important technology. This includes: wafer thinning, bonding techniques, TSV Formation and metalization, the production of electrical isolation layer. TSV formation is one of the key processes. Taking into account factors such as cost, precision control, generally tend to use dry etching production of TSV. The etching process is more complicated, the location of the through hole type of three-dimensional IC, density, and size (including the depth of the hole and the aperture) is different. Through Hole technology need to be able to meet on the shape of the contour control (including control of inclination, shape, surface roughness, after etching, etc.), while the process reliability, practicality and repeatability, finally, the cost should be reasonable control. The purpose of this paper is to reactive ion etching technology, used in IC device the TSV wafer level packaging technology. In the study, the encapsulation step, first of all covered with a protective layer on the wafer bonding techniques; then thinning the wafer from the silicon surface to a desired thickness; made from the silicon surface with a reactive ion etching of TSV ; regional coverage insulating layer; Thereafter, the re-distribution of metal wiring layer is formed on the wafer; Finally, dicing the wafer into individual chip package. Experiment, using reactive ion etching to achieve TSV, through-hole morphology were analyzed by SEM (Scanning Electron Microscope, scanning electron microscopy) machine, resulting in the optimization of the gas flow, pressure, power, time parameters. Eventually, after the etching process parameters optimized, by etching, to achieve the production of TSV. Experiments show that this etching process used in conjunction with other relevant production process, able to complete the TSV wafer-level packaging. Samples were randomly selected for testing, the results meet the requirements.
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