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Research on Policy of Low-Power Based on Scratchpad-Memory

Author: YuanMingJu
Tutor: HuZhiGang
School: Central South University
Course: Computer Science and Technology
Keywords: Timestamp Circuit Activity SPM allocation Dynamic power Layout Optimization
CLC: TP368.1
Type: Master's thesis
Year: 2010
Downloads: 24
Quote: 0
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Abstract


With the development of the semiconductor manufacturing process and the LSI design capability , embedded device volume is getting smaller and smaller , more powerful functions , which led to the issue of energy consumption of the system have become increasingly prominent . Studies have shown that the energy consumption of the storage subsystem is an important source of energy consumption of the entire system - on-chip , reducing the energy consumption of the storage subsystem can effectively reduce the energy consumption of the entire system - on-chip . As an on-chip SRAM , Scratch -Pad Memory (SPM) because of its small size , low power consumption , fast access , real - time guarantees and the chip inside and outside the unified addressing the advantage gradually instead Cache trend . This paper focuses on this theme, focusing on how to take advantage of the SPM Energy Optimization for embedded systems , reducing energy consumption due to storage access , SPM dynamic management strategies can reduce the power consumption of the storage subsystem compile and discussed the SPM layout to optimize system power consumption . Only consider a separate dynamic management strategies for existing SPM program instructions or data variables as placed in the SPM candidates this situation , a dynamic management algorithm based on the timestamp of the SPM . Through analysis of the dynamic invocation of applications , the establishment of the control flow graph based on the extension of the program calls the relationship and timestamp , considering the global variables , stack variables , data , program code on the energy consumption of the system , at each point in the program to choose the right the program elements placed SPM to reduce the energy consumption of the storage subsystem . For the existing SPM low power management strategies focus is how to maximize repeat visits in the SPM without considering the different SPM address to access the sequence of power consumption , a circuit-based activity SPM layout optimization strategy. The optimization strategy the basic SPM management strategy based on , by reorganizing the instruction and data layout, reducing circuit Activity of these storage objects when access to the SPM address lines , thereby reducing power consumption in SPM . The simulation experimental results show that , compared with the existing SPM static management strategies , dynamic management strategy based on the timestamp of the SPM , the same application power consumption can be reduced up to 31.3% in the case of the same capacity and limited SPM . Compared with the basic layout optimization strategy , based on the the circuit activity SPM layout optimization strategy can be reduced by an average power consumption by more than 15% .

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CLC: > Industrial Technology > Automation technology,computer technology > Computing technology,computer technology > Micro-computer > A variety of micro-computer > Microprocessor
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