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Highly Accelerated Stress Test Technique on High-density Packaging Integrated Circuits

Author: ZhangShanLun
Tutor: LiBin；LaiPing
School: South China University of Technology
Course: Microelectronics and Solid State Electronics
Keywords: Highly accelerated stress test Online monitoring Temperature cycling Vibration stepping Failure analysis
CLC: TN405
Type: Master's thesis
Year: 2010
Downloads: 158
Quote: 0
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Abstract


Highly accelerated stress test is important research direction of the field of reliability testing. Internal flaws and weaknesses of products can be excited quickly and efficiently by HAST. Products limits of tolerance of stress can be identified. Test efficiency can be increased Substantially. Product development costs can be reduced. China has not carried out systematic work for electronic components on highly accelerated stress test. Systematic test method and corresponding data accumulated of stress test limit is lack. therefor, In this project highly accelerated stress tests and failure research are carried out for high density packaged IC. The study includes highly accelerated stress test method,monitoring design,failure analysis techniques,simulation of test section.Highly Accelerated stress tests are carried out for high density packaged typical micro circuits. Temperature step test、temperature cycle test、vibration step test and compound stress test are executed for each sample. IDDQ and Pin in-situ monitoring instrument are designed to be used to monitor sample Pin Parameters.Performances changes by stress are researched for five kinds of samples. Failure mode and mechanism are studied which is exposured by stress. Plastic packaged samples’ layered cracking and bond off are exposured. Ceramic packaged samples’ bond compound grouth、conductive adhesive cracking、aluminum oxide and pin fracture are exposured. Mechanism including the proliferation of growth in compounds and bond failure under thermal stress and mechanical stress are analyzed.The results show that Temperature cycle test is the The most effective high accelerated stress test for high-density packaging IC. Efficient Temperature profile Apply -65℃~165℃to be Endpoint temperature、15min to be Holding time、6 to be cycles.Finally, optimization of the temperature cycle test profile is discussed by ANSYS finite element analysis. Comprehensive analysis was carried out combined with high accelerated stress test results. Analysis Conclusion is that for high density packaged IC, cycle of effective screening test is 3-4. The highest temperature change rate of test equipment should be used. Low-temperature holding time should be 10-20. high-temperature holding time should be 4-5. The results show the correctness of Efficient temperature cycling profile by test.Thesis results provide technical reference for HASS on high density packaged IC.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Microelectronics, integrated circuit (IC) > General issues > Manufacturing process
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