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Physical Design of a Chip on NUCSoC

Author: ZhangZhi
Tutor: SangHongShi
School: Huazhong University of Science and Technology
Course: Pattern Recognition and Intelligent Systems
Keywords: Physical design Layout planning Clock tree synthesis Physical verification
CLC: TN47
Type: Master's thesis
Year: 2011
Downloads: 19
Quote: 0
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Abstract


IC physical design is integrated gate-level netlist converted to actual traces territory bridge chip circuit design and chip manufacturing , it is not only related to the functionality of the integrated circuit is correct or not , but also related to the integrated circuit performance and cost , integrated circuit physical design aspects include : the logic synthesis , floorplanning , clock tree synthesis , wiring planning, physical verification . The this article chips for NUCSoC , based on the analysis of traditional physical design flow , the use of a low -power , high-performance timing closure layout design method . First , the block diagram the NUCSoC chip analysis of various clock domains timing , physical synthesis ; Secondly , the completion of data preparation , layout planning , clock tree synthesis , the wiring plan NUCSoC chip placement and routing design ; Finally , the territory after the place and route planning reasonable verification of timing verification , power verification , layout , DRC verification and LVS verification . Power optimization , the first clear power optimization goals , and then analyze the factors that affect the power consumption of the various stages of optimization , including : adjust the layout in the planning stage PAD , hard macrocell , the standard unit of physical location , planning of power network insert clock buffers of different sizes and route planning stages of clock tree synthesis stage set crosstalk parameters apply this method to reduce power consumption by 10.92% . Timing optimization , first clear timing optimization goals , and then analyze the factors that affect the timing of the various stages of optimization , including : clock tree synthesis stage and route planning stage insert clock buffers to optimize the size of the device , and ultimately achieve the establishment of NUCSoC chip time, hold time , maximum fan-out , transition time and load capacitance to meet the design requirements , to apply this method to the timing closure margin of 6% . Use the ATE equipment convective piece back chip test clock frequency of 100MHz kernel consumes 199mW , the chip consumes 255mW , equivalent logic gates to 457k area was 2.4 mm × 3.58mm for 640 × 480 × 14 bits images up to 100 per second of data through rate to meet the requirements of real-time applications , the test results show that the effectiveness of the above methods .

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Microelectronics, integrated circuit (IC) > LSI,ultra LSI
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