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Design of the Data Receiver for High-speed Serial RapidIO Interface

Author: SuYuan
Tutor: YiXiaoFei；MaZhuo
School: National University of Defense Science and Technology
Course: Software Engineering
Keywords: Serial Interface RapidIO Programmable equalizer Sense amplifier Multi- phase data extraction
CLC: TN851
Type: Master's thesis
Year: 2010
Downloads: 254
Quote: 0
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Abstract


RapidIO is a system-level interconnect technology, mainly for high-performance digital signal processing systems and embedded systems interconnect traffic. It provides switched interconnect rather than bus-based data transmission standard methods, the use of high-performance interface technology can achieve 10Gbps transfer rate in four of the differential line, but higher than the 10 Gigabit Ethernet, PCI Express the transmission efficiency. RapidIO better consider routing, switching, fault-tolerant error correction, ease of use, you can achieve high-performance hardware-based reliable data transfer. This paper studies the basic requirements of the Serial RapidIO Physical Layer Specification of interface design; Then, based on the study of the high-speed signal transmission theory, analysis of the behavior of the transmission line and a variety of non-ideal factors affect signal integrity; final design of high-speed serial RapidIO transmission system circuit and layout of the data receiver. It includes programmable equalizer sense amplifier sampling circuit, differential-to-single-ended circuit and serial to parallel module. The Equalizer In this paper, the design of the core, because the signal after transmission line, high frequency attenuation is more serious, making the receiver receives the signal rise / fall time becomes longer, can easily cause inter-symbol interference, resulting in the error rate increased. Equalizers are capable of high-frequency component compensation received signal, increase the high-frequency component in the signal component to restore the quality of the signal, so its performance is related to the whole receiver is able to correctly identify the received signal. The data sample used in the overall structure of a multi-phase data extraction technology, with four phase clock (recovery from CDR) to sample the serial data, so you can use the low clock speed sampling the high-speed serial data stream. Sense amplifier sampling circuit is carefully designed, especially the size of the transistor in the circuit parameters to continuously optimize and adjust the territory should pay particular attention to the matching of the device, reducing process errors. Differential to single-ended circuit structure of the SR flip-flop, the use of cross-coupled NAND gate. Serial to parallel shift register is used to achieve, by displacement, under the control of the bit clock of the serial data to be saved into a serial connection of the D flip-flop, then these data sync output under the control of the fifth of the word clock frequency obtained completion of a serial to parallel conversion to the parallel output register.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Radio equipment,telecommunications equipment > Receiver equipment, radio Radio > Receiver: the form of points
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