Dissertation > Excellent graduate degree dissertation topics show

The Design of High-speed Low-power Comparator

Author: YouHengGuo
Tutor: ZhuangZuoZuo;WangJin
School: Xi'an University of Electronic Science and Technology
Course: Software Engineering
Keywords: Comparator Pipelined-ADC Preamplifier-latch high-speed,low-power
CLC: TN792
Type: Master's thesis
Year: 2011
Downloads: 465
Quote: 0
Read: Download Dissertation

Abstract


Analog-to-digital converters (ADCs) are important building blocks in many electronic applications.With the rapid development of video and communication technology,high-speed,medium-resolution ADCs requirements are increasing.Various architectures have been used to deliver these high-speed,medium-resolution ADCs.Of these,pipeline architecture has proven to be the most efficient for applications.The comparator is a crucial part of ADC.Its speed and power have great impact on the characteristic of the whole ADC.Being one of various architectures,preamplifier-latch is widely used as high-speed comparator due to its high-speed,low-power and small offset voltage. Based on preamplifier-latch comparator, adopted TSMC 0.13μm CMOS process,a high-speed,low-power comparator applied for pipelined-ADC is proposed in this paper.Besides,the layout was designed and taped out. This comparator consists of three blocks:latch,pre-amplifier and switched capacitor circuit.With fast response and low power consumption,latch has large offset voltage and kick back noise.Pre-amplifier can increase the speed of the comparator.Besides,it can also reduce offset voltage and inhibit the kick back noise.In order to reduce the offset voltage further,auto-zero technology was used by adding switched capacitor circuit,then the comparator can compare the differential signal.The post simulation result showed the power consumption of the comparator was 0.505mW at 500MHz and 0.336mW at 125MHz.Experimental results showed that the power consumption was 0.36mW at 500MHz and the offset voltage achieved 5mV.The comparator satisfies pipelined-ADC performance requirements when the input voltage rang is 450mV~950mV.

Related Dissertations

  1. Research and design difference time-domain comparator - based successive approximation analog-to-digital converter,TN792
  2. Design of Low Power Pipelined ADC for Motion-Detection CMOS Image Sensor,TN792
  3. Design and Realization of High-speed and Low-power SRAM,TP333
  4. Design of Low Power Pipelined ADC for CMOS Image Sensor,TN792
  5. The design of high - speed low-power SRAM in 90nm process,TP333
  6. Design of an 8-bit 320-MS/s Cascaded Folding and Interpolating ADC,TN792
  7. Anti-irradiation 4K × 32bit SRAM Research and Design,TN47
  8. Research and Design of low-power pipelined ADC,TN792
  9. Design and Performance Analysis of a Readout Circuit for Low Power Silicon Detectors,TN303
  10. Research and Design of Low Power Pipelined ADC in 65NM CMOS Technology,TN792
  11. Design of Asynchronous Low-power LDPC Decoder,TN764
  12. A Heat Monitoring System Based on a Non-magnetic Heat Meter,TP274.4
  13. Design of Main Circuits in a Low-power Pipelined Analog to Digital Converter,TN792
  14. Design and Research of Nano-CMOS High-speed Low-power Adder,TN432
  15. 1Mb High Speed Low Power SRAM Design,TP333
  16. Research of 10-bit 50MS/s Pipelined ADC for Embedded Use,TN792
  17. Applied to a CMOS image sensor of low power pipelined ADC,TN792
  18. Research on the Design of 4-bit High-speed and Low-power Microcontroller,TP368.1
  19. Study of A Readout Circuit for CZT Surface Element Pixel Arrays Nuclear Radiation Detector,TL822
  20. Design and Realization of High Speed Pipeline ADC,TN792
  21. The Design of a High Speed Pipelined ADC,TN792

CLC: > Industrial Technology > Radio electronics, telecommunications technology > Basic electronic circuits > Digital circuits > Digital-analog , digital to analog conversion circuit
© 2012 www.DissertationTopic.Net  Mobile