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Researches on VLSI Design and Implementation of Intra Prediction in H.264 Video Coding
Author: FengYuLi
Tutor: XiaoZuo
School: Xi'an University of Electronic Science and Technology
Course: Communication and Information System
Keywords: Video Coding H.264 Intra prediction VLSI
CLC: TN919.81
Type: Master's thesis
Year: 2011
Downloads: 41
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Abstract
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With the rapid development of information technology , human society has entered a whole new era of multimedia , multimedia communication has also become a way of human communication is very important . H.264 video codec standard for its efficient compression performance , good image quality , better network -friendly and better error resilience performance , and growing as a mainstream video standard is widely accepted . Compared to the previous video standard H.264 video coding standard , introduced in the details of the deal , some of the new algorithm , such as multi-mode motion estimation and intra prediction , based on the contents of the variable-length encoding , 4 × 4 2D integer transform . Overall , H.264 greatly improve performance , while also greatly increase the computational complexity , which has brought a great deal of difficulty to the hardware design and implementation . FPGA-based system design and video codec chip also has a strong application . This article describes the H.264/AVC video compression codec standards as well as in video real-time H.264/AVC HDTV encoder intra-frame coding module hardware implementation aspects of the research , the focus is in the H.264/AVC intra prediction algorithm VLSI implementation of its hardware module is part of the in-depth study proposed a parallelized operation structure . Processing of some prediction algorithm using the structure of the parallel processors , not only shorten the processing time and improve the processing rate , and at the same time saving system resources , making the time of the intra prediction coding a macroblock completed up to only 1136 clock cycle can achieve the requirements of real - time decoding . Of these predicted modules achieved with VerilogHDL language , and success of the program in Xinlinx Virtex5 xc5vlx330t FPGA good real-time performance .
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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Communicate > Image communication, multimedia communication > Image coding
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