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Design and Implementation of the PIC Detector in Code Division Multiple Access System

Author: ZhaoYanLong
Tutor: LiYanPing
School: Taiyuan University of Technology
Course: Circuits and Systems
Keywords: Multi-user detection Parallel interference cancellation FPGA Hebb learning rule
CLC: TN929.533
Type: Master's thesis
Year: 2011
Downloads: 33
Quote: 1
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Abstract


CDMA communication system, multiple access interference became key factors affect the performance and capacity of the communication system, how to inhibit or reduce the impact of multi-access interference has become a hot research topic. Multi-user detection techniques to fully take advantage of a variety of multi-access interference known to detect the user information to treat joint detection, which received good inhibition and offset the effect of multiple access interference, and also to some extent inhibited distance effect, to further explore the CDMA communication the development potential of the system. This study focused on the FPGA implementation of the multi-user detector in DS-CDMA system. On the basis of previous studies, the first FPGA internal structure and design process, combined with the actual design examples about several data flow control technology in the design of FPGA development. Then, study the principle and working process of the application Hebb learning rule partial parallel interference cancellation detector from the FPGA hardware design point of departure for dismantling and simplify the algorithm. Completed application Hebb learning rule partial parallel interference cancellation detector FPGA design, and the experimental board-level debugging, verify the correctness of the design combined with the detector to achieve in this paper the characteristics of the hardware resource utilization and system performance compromise FPGA design and implementation process, the following improvements: (1) using a variety of data flow control technology, such as pipelining technology, ping-pong operation and string and convert technology, starting from the actual situation of the hardware in the speed and area between a reasonable choice, and greatly improving the data processing speed of the system; (2) use the Twos operation instead of the matched filter in the multiplication operation, and overcome the hardware multiplication delay Japanese hardware consumes a big problem; (3) Data Extension the divider clock delay and delay line combination when used, significant savings in the hardware storage resources consumed by the hardware data delay; (4) a reasonable set of effective data acquisition time to overcome data chattering; take full advantage of BlockRAM data storage and a latch function, to avoid the delay of the distribution of RAM for data storage may bring; (5) on the basis of the reference clock of the system, according to the processing speed of the different modules it is assigned a different clock frequency, and by improving the sentinel process fractional clock frequency method to reduce the the module processing delay, with the tacit understanding of each module; (6) said data corresponding calibration and a reasonable trade-off for different situations, without the loss of accuracy of the premise, as much as possible to improve the data processing speed.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Wireless communications > Mobile Communications > Cellular mobile communications systems (mobile phones, mobile phone handsets ) > Code Division Multiple Access (CDMA) mobile communication
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