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A Hardware Design of IEEE1588 Precision Clock Synchronization Protocol

Author: TaoLi
Tutor: ZhangYan
School: Harbin Institute of Technology
Course: Microelectronics and Solid State Electronics
Keywords: IEEE1588 PTP Clock synchronization
CLC: TN915.04
Type: Master's thesis
Year: 2011
Downloads: 234
Quote: 1
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Abstract


With the rapid development of network technology, the application of frequency and time synchronization requirements as well as its increasingly demanding accuracy requirements. Issues such as the high cost of political and security risks of the GPS makes use of the ground cable transmission link transmission frequency and time signal of the demand came into being. IEEE1588 precision clock synchronization technology by virtue of its absolute advantage in accuracy, the salient points of the solution methods that reduce the impact of the network formation jitter delay, get more and more attention and widely used in the communication network. This paper first introduces the background of the clock synchronization demand at home and abroad of the status quo. PTN packet switching technology described principle, comparing the advantages and disadvantages of several PTN network clock synchronization technology. And detailed analysis of the the PTP protocol defined in the IEEE1588 clock synchronization standard depth study IEEE1588 system structure, the PTP device type and PTP synchronization mechanism. On this basis, a program based on the the PTP protocol of time and frequency synchronization hardware using Verilog hardware programming language implementation of the entire circuit. After each of the function module is designed in the PTP clock synchronization circuit elaborate, given the realization structure diagram. Finally, build a self-test platform for functional testing, the preparation of a comprehensive simulation stimulus, and confirmed its function properly, and RTL simulation results are given. Use the Quartus Ⅱ tools to complete the synthesis and layout, and according to the report of the performance indicators, further optimization of the design, and finally achieve a clock frequency of 200MHz, 5G processing wire-speed performance. The design is characterized by: one can support both the frequency and time synchronization. IEEE1588 clock synchronization design usually only support time synchronization, time synchronization support the provisions in the agreement not only in the design, by sending sync packets generated timestamp to achieve frequency synchronization. Support both step mode and two-step model based on the the IEEE1588v2 supports transparent transmission clock and delay measurement mechanism. Due to the implementation complexity, universal programs are only one step mode. This article by groups of storage, while reading the comparative and the source port number for the address index to store / read the serial number of the message, and to achieve a fast matching s source port number, and serial number, in order to achieve the two step-by-step mode processing functions. Taken on the hardware implementation of a multi-stage pipeline structure to ensure that every 11 auctions a message, in order to achieve the 200MHz frequency 5G line speed indicators.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Communicate > Communication network > General issues > Communication protocols, communication protocols
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