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Convolutional code decoding algorithm and its FPGA implementation

Author: YeFei
Tutor: ZhengChaoXia
School: Huazhong University of Science and Technology
Course: Software Engineering
Keywords: Channel coding Convolutional code Viterbi decoder Field Programmable Gate Array
CLC: TN791
Type: Master's thesis
Year: 2011
Downloads: 176
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Abstract


As a digital baseband processor in a wireless communication system of error control coding is one of the most popular techniques , Viterbi decoding algorithm based on error correction convolutional code has been widely used. Wireless LAN as the main trend of future mobile communication , is moving in high speed, low power consumption, access to flexible direction. IEEE802.11 protocol uses the concept of the key technologies 4G -OFDM ( orthogonal frequency division multiplexing ) technology to achieve high-speed wireless LAN communication . Viterbi decoder under the agreement as an important part of the digital baseband processor , its speed and power performance of the whole system has a vital role in the success or failure . In this paper, IEEE802.11 protocol for wireless LANs digital baseband system project as background, studied and designed in this context of convolutional codes based on OFDM system codecs . In this paper, channel coding and decoding of the basic concept began , highlighting the Viterbi decoding algorithm based on the basic principles and convolutional code encoding and decoding process , on this basis , the design of codecs RTL level circuit and its functional emulation. After the presentation in the current widespread use of digital circuit design field-programmable gate array (FPGA) design methods, and use of Altera 's DE2-70 FPGA hardware development platform for the design of a comprehensive and validated , given the translation transcoder resource consumption and speed reference value . The design of the main innovations and work are: ( 1 ) improved Viterbi decoder plus selection structure , through the use of four parallel butterfly computing unit, reducing power consumption while also reducing the cost of hardware resources ; ( 2 ) back through the Viterbi decoding process of introducing pong operation , reducing power consumption while also reducing the decoding delay time. The design of the codec has been involved in the entire OFDM digital baseband transmit and receive side 's overall debugging , debugging results demonstrate that the design is functionally correct.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Basic electronic circuits > Digital circuits > Logic circuits
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