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VHDL-based programmable logic device virtual experiment platform for the design and implementation of
Author: LiuYuHuan
Tutor: YuJunQing
School: Huazhong University of Science and Technology
Course: Computer technology
Keywords: Virtual Experiment Platform Programmable Logic Devices Simulation technology Compiler Event-driven simulation algorithm
CLC: TP311.52
Type: Master's thesis
Year: 2011
Downloads: 23
Quote: 0
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Abstract
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Virtual experiment is the use of multimedia, computer simulation and virtual reality technology to achieve a virtual lab environment , the experimenter in an interactive manner experimental operation , can be like in a real environment as a pilot project scheduled to complete a variety . It provides a method of operation and the actual experiment similar practice experience , to a certain extent to solve the traditional experimental teaching time limit , space constraints and resource constraints and other issues. Thesis, VHDL-based programmable logic device virtual experiment platform for the design and implementation of programs . By analyzing the characteristics of VHDL synthesizable extracting a virtual experiment platform for VHDL subset given VHDL-based programmable logic device virtual experiment platform design. Platform consists of VHDL program translation module and analog scheduling module of two main parts . Translation module is the core of VHDL compiler will translate user-written VHDL source code is converted to equivalent C language description of the resulting number of C program files ; simulation scheduler module by improving the traditional event driven simulation algorithm, the translation module to get C files for dynamic scheduling to achieve the static description of the dynamic behavior of the circuit simulation , and ultimately generate a link library file . The C source circuit simulation scheduler description file link library files, connect through C compiler to generate the final executable simulation program. Using Flex Builder and VC to achieve a B / S structure of the programmable logic device virtual experiment platform , the platform through a typical experimental sample was verified . The results indicate that the system to achieve the desired design requirements , according to VHDL source input device to establish the correct functional simulation model , the device can be customized to meet the interactive features of the virtual experiment platform requirements , programmable logic devices to meet course experiment application needs.
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