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Error Control Scheme for High Performance Network-on-Chip Routing

Author: WangBin
Tutor: MaoZhiGang;XieZuo
School: Shanghai Jiaotong University
Course: Circuits and Systems
Keywords: Network on Chip Reliability of the coding Asynchronous wormhole router Four-phase two-track handshake protocol Delay insensitive
Type: Master's thesis
Year: 2011
Downloads: 17
Quote: 0
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Network - on - chip (NoC) system is the focus of current research , it is a higher level of larger systems - on - a - chip , the core idea is the computer network technology to the chip design to solve the multi - IP core network interconnection architecture issues . On-chip interconnect is one of the NoC chip key , its normal communication relationship to the normal function of the chip , but the As process geometries shrink , the crosstalk noise on the interconnect has been seriously interfere with the transmission of signals , while reducing the chip's operating frequency. In order to ensure the correctness of the interconnected transmission as well as network - on - chip high - throughput needs , design a full set of on-chip network reliability transmission scheme . As a bridge, a four-phase two-track handshake protocol design an error-correcting codes , asynchronous wormhole routing node , as well as a 4x4 mesh -based on-chip network structure . Use of a simple packet Hamming code word error correction of the channel transmission capacity of up to 10 bits , using the replica code to substantially eliminate the impact of the crosstalk noise , C unit by a simple logic circuit to the physical layer of the data is converted into a high - level protocol data to facilitate the routing nodes forwarding data . Design a low-power , delay insensitive asynchronous router for multi- clock domain channel fragmentation and advance water technology and accelerate the routing nodes , making it the highest throughput of up to 2.3GB / s . Organizational form and send the rules of the proposed design of the package , making the network bandwidth utilization improved significantly , the most obvious effect of a small packet , about speed three times .

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Microelectronics, integrated circuit (IC) > LSI,ultra LSI
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