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Low leakage power trigger Research and Application

Author: ZhangZuo
Tutor: HuJianPing
School: Ningbo University
Course: Circuits and Systems
Keywords: Energy recovery Leakage power consumption Trigger Sequential Circuits
CLC: TN783
Type: Master's thesis
Year: 2011
Downloads: 53
Quote: 0
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Abstract

In 1965, Intel co-founder Gordon E. Moore predicted IC industry development law: the density of integrated circuits quadrupled every three years, every three years, feature sizes shrink (?) Times. large. Leakage power in the total power consumption in the proportion is increasing, while the previous researchers concern is how to reduce dynamic power, leakage power consumption of neglect. At present, the urgent need to reduce the chip leakage power consumption in the context of the leakage power designers to do a more detailed investigation, made a variety of leakage power reduction techniques, such as multi-threshold technology, transistor stack technology. This will be the basic timing circuit energy recovery unit - the trigger for the study investigated under deep submicron technology reduces IC leakage power consumption. The main contents include the following components: first, deep sub-micron process introduced under three main leakage current: sub-threshold leakage current, gate leakage current and the drain-source - substrate reverse biased junction current, and details Their mechanism of action. Increasing leakage current, leakage power reduction techniques evolved, the paper analyzes the existing conventional CMOS leakage power reduction techniques. Leakage power reduction techniques can be divided into active leakage power reduction techniques and sleep leakage power reduction techniques. Activities leakage power reduction techniques including stack and P-type transistor circuit design technology; Sleep leakage power reduction techniques, including multi-threshold techniques. Secondly, the subject of innovation focused on energy recovery timing circuit leakage power reduction technique research, thus detailing several typical energy recovery circuit and triggers structures for these types of energy recovery circuit work Principles and triggers structure are discussed. And use a variety of activities leakage power reduction techniques for the design optimization of the trigger was investigated in the timing circuit design system application. Respectively, the activities of the circuit leakage power measurement method, the energy recovery circuit timing channel length biasing techniques and energy recovery of P-type sequential circuit design techniques are discussed. This paper selects ECRL and CPAL both exploration and research for the typical adiabatic logic circuit channel length biasing techniques and P-type design techniques, the results proved to the realization of the program in the total power dissipation and leakage power consumption have been effectively reduced . Final analysis under the dormant deep submicron technology reduces leakage power in the application of sequential circuits. CPAL circuit to trigger as the research object, verify power control technology reduces energy recovery sleep timing circuit total power dissipation and leakage power dissipation effect.

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