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Research on the Fault-tolerant Design of Digital System Based on Dynamic Partial Reconfiguration of FPGA

Author: LiuZuoWen
Tutor: YaoZuo
School: Nanjing University of Aeronautics and Astronautics
Course: Measuring Technology and Instruments
Keywords: FPGA Dynamic part of the reconstruction Fault-tolerant Modular design Bus macro EAPR design
CLC: TN791
Type: Master's thesis
Year: 2011
Downloads: 107
Quote: 1
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Abstract


Field-programmable gate array (FPGA) can not only use the software programming method to complete the entire hardware configuration of the circuit functions , and can be reprogrammed and dynamic reconfiguration capability in space exploration , aerospace , remote sensing, telemetry , industrial control , medical , communications , etc. the field of general application . FPGA dynamic reconfiguration technology has been widespread concern caused by domestic and foreign scholars , and FPGA-based fault-tolerant system design technology has important theoretical significance and practical value . In this paper, fault - tolerant design techniques to dynamically reconfigurable FPGA - based digital systems , the main contents are as follows : ( 1 ) fault-tolerant reconfigurable digital system based on the dynamic part of the overall design of the establishment of the program and its reliability analysis . To improve the reliability of the FPGA harsh working environment , this paper based on FPGA dynamic part of the reconstruction of the D / the TMR system design , normal working hours DMR system , has a low area overhead and power consumption ; when the system fails, the FPGA portion of the dynamic reconfiguration technology switch to the TMR system , no additional fault detection and location circuit . From the theoretical analysis of the reliability of the system , compared with traditional DMR and TMR system . (2) Cord - encoder and 2 -bit multiplier , for example , to verify that the system program . Between the first 8 Cord - encoder , for example , in accordance with the multi-level structure is divided D / TMR system to complete the design of the module ; selection of newer SLICE - based design , using FPGA Editor design tools to create a module and module the fixed bus macro communication design ; use of modular design process is completed based on the design of the encoder D / TMR system ; using Xilinx the recommended EAPR design method re- design, analysis advantages of EAPR design . Finally, we use a modular design process is complete multiplier design based on the D / TMR system , verify the feasibility of the experimental results .

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Basic electronic circuits > Digital circuits > Logic circuits
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