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Research and Implementation of the Parallel Storage System Based on NAND FLASH

Author: JiaYuanQuan
Tutor: XiaoZuo
School: National University of Defense Science and Technology
Course: Computer Science and Technology
Keywords: NAND FLASH Multiple parallel storage system Bad block handling policy Out-of-order execution
CLC: TP333
Type: Master's thesis
Year: 2011
Downloads: 49
Quote: 0
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Abstract


With the rapid development of information technology, the requirements of the users of the data storage capacity and speed increasing challenges, large capacity and high reliability requirements of the storage system to the storage area, the traditional computer storage systems using mechanical disk device due to the amount of storage I / O access latency and other issues become the limit storage system performance bottlenecks. At the same time Flash (FLASH) as a non-volatile storage media with fast read and write, nonvolatile data storage capacity, non-mechanical mechanism, low-cost manufacturing, good parallelism potential characteristics, through progressive development and numerous technological change, gradually revealing a huge advantage by scholars at home and abroad as well as the attention of the industry, or an alternative to traditional disk. Paper designs and implements multiple parallel storage systems based on NAND FLASH experimental platform FPGA development board, the large-capacity NAND FLASH chip Samsung establishment of a multi-channel parallel storage systems for the storage unit configuration, the experiments show that the system has good parallel, high-speed, reliable security features. The main work and innovation of the papers include: FLASH related technologies and FLASH memory status quo detailed study raised the possibility of the establishment of NAND flash storage systems, and build the advantages of the system, and will encounter problems; NAND FLASH chip internal structure and interfaces detailed study of the feasibility study multiple parallel storage systems and objectives. According to the structural characteristics of the FLASH chip, designed NAND FLASH-based multi-channel parallel storage card and board complete storage system based on hardware module design, including the main logic module design, the ECC module design, intersecting switch modular design, the transmitter module of the out-of-order design. . NAND FLASH-based multi-channel parallel storage system complete system of data read, write, delete operation simulation and experimental development in the FPGA board to ensure the normal operation of the system data access. FPGA experimental platform to test the system, the access rate of 600M 4 * 8G FLASH card. The introduction of multi-channel system for large-scale solid-state flash memory parallel technology to bring the bad blocks, an efficient bad block management strategies taken parallel storage bad block coding technology to save a bad block table storage space, reduce bad block handling functions consumption, reconfigurable processing technology is an effective solution to a bad block problem of the system in the same location at the same time take the bad block table. FLASH chip sequence command mode theory, the FLASH command launched by the out-of-order execution model, and design based on out-of-order launch NAND FLASH memory controller.

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CLC: > Industrial Technology > Automation technology,computer technology > Computing technology,computer technology > Electronic digital computer (not a continuous role in computer ) > Memory
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