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Design and Implementation of JPEG Encoder Based on DE2 Platform

Author: XuLong
Tutor: SuYuTing
School: Tianjin University
Course: Signal and Information Processing
Keywords: JPEG FPGA DCT DE2
CLC: TN919.81
Type: Master's thesis
Year: 2008
Downloads: 224
Quote: 5
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Abstract


The image processing and compression techniques play an important role in the development of multimedia techniques. In the field of image compression, the still images compression standard JPEG is widely applied for its excellent performance.In recent years, the specific image compression chips have been increasingly used by more and more electronic products. JPEG compression chips have a large number of applications in consumer electronics such as digital cameras. The research of image compression chips has become the new focus in information industry.This paper describes a design for JPEG Baseline compression encoder, based on DE2 FPGA development board of Altera Corporation. The FPGA used in the design is EP2C35 of CycloneⅡseries. The architecture of the two dimensional discrete cosine transform (DCT) is based on the conventional row-column decomposition method. The implementation of DCT by fast algorithm greatly reduces the hardware complexity, performs high throughout. It has the advantages of real-time and high accuracy. In the quantization module, a custom divider is used to reduce the division operation time. The whole design massively uses pipeline optimization,raising the system’s operating frequency.The JPEG Baseline encoder is implemented in standard hardware description language Verilog. The whole design is based on the reusable IP technology,each module can be synthesized and simulated. The results of synthesis and simulation indicate that this JPEG encoder, based on CycloneⅡseries FPGA, consumes less FPGA hardware resources, and achieves a high operating frequency.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Communicate > Image communication, multimedia communication > Image coding
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