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Side wall TEOS - SiO 2 thin layer removal and re- deposition

Author: YuXinBo
Tutor: LiBingZong；FanJianGuo
School: Fudan University
Course: Electronics and Communication Engineering
Keywords: Side wall TEOS - SiO2 Dust particles
CLC: TN405
Type: Master's thesis
Year: 2008
Downloads: 25
Quote: 0
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Abstract


In the field of integrated circuit manufacturing, the transistor is an application of the circuit of one of the main device, it is self-aligned source-drain-gate process is the key of the transistor fabrication. In deep-submicron technologies, small size, the lightly doped source-drain (LDD) is an important part of the MOS tube and its associated sidewall spacer technology is the key to the effectiveness of the influence transistor features. For large-scale production of integrated circuits such high precision micromachining, it is characterized by a long process, can be up to thousands of processes, so the yield is good or bad depends on every process. How to improve the product yield economic benefits will have a huge impact, so we LDD key process in this section of the side wall TEOS were studied. The side walls TEOS-the SiO 2 thin layer removal and re-deposition mainly the polysilicon sidewall process in terms of the 8 inch 0.18um logic products, by improving the process of polysilicon sidewall to improve product yield. 0.18um logic technology, side walls usually have three different layers of the structure that is composed of SiO 2 -SiN-SiO 2 , wherein the third layer of the thickness of the side wall TEOS the largest and most vulnerable to dust particles. When the third tier side wall of TEOS dust particles subjected to a certain amount or volume of contamination, the affected chip unit reaches a certain percentage, the entire wafer have to be scrapped, this is not a small loss for the company. Therefore, our experiment is carried out against the sidewall spacer TEOS. Specific experimental procedure, we chose a large number of dust particles deposited End spacers TEOS wafers, the first sidewall spacer is removed with hydrofluoric acid TEOS, and then re-deposition of TEOS spacers. When the wafer is completed all the process in WAT ① testing of the product yield. All test data to meet the requirements, then remove the side wall the TEOS and re-deposition side wall of TEOS product does not cause low dose rate, that is \> TLC removed and re-deposition of the experiment is successful. Side wall TEOS-the SiO 2 thin layer of removal and re-deposition \how this process and the economic losses caused; also can be applied to the wafer TEOS deposition process of the side wall was a small amount of dust particles but does not meet the criteria for scrapping, in order to improve the process of TEOS side wall, to improve device performance and reduce potential risks, thereby increasing the yield of wafer products.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Microelectronics, integrated circuit (IC) > General issues > Manufacturing process
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