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NoC architecture performance assessment and the design of communication components

Author: YangZhiFeng
Tutor: TianZe
School: Northwestern University
Course: Microelectronics and Solid State Electronics
Keywords: Network chip (NoC) Performance Evaluation Communication Components Globally asynchronous locally synchronous (GALS)
CLC: TN47
Type: Master's thesis
Year: 2009
Downloads: 87
Quote: 2
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Abstract


Currently , semiconductor process node has been reduced to 50nm, the number of transistors that can be integrated on a single chip has exceeded 1 billion . Technological progress makes made ??possible by systems with complex functionality on a single chip . On the other hand , the consumer function is more powerful , the bigger integrated circuits demand growth , combined with the drawbacks of traditional bus architecture SoC ( system - on - chip ) have become increasingly apparent . In this context , people learn from computer systems from stand-alone to the historical experience of the network development , trying to solve the problems encountered in the integrated circuit design based communication NoC ( network chip ) . NoC research and applications is still in its infancy . The scope of its research , the main content of the study : topology , communication protocols, the basic component libraries and EDA theory and tools . This article summarizes the NoC theoretical system on the basis of , and focuses on the performance evaluation of NoC architecture and design of NoC communication components . The NoC architecture performance parameters , the topology of several common communication network simulation software NS2 simulation process . Trace files obtained by the simulation of awk processing, network latency , the quantitative value throughput and packet loss rate , xgraph and gnuplot drawing tools to draw out comparison . In addition , the paper describes the the NoC communication components based on a two-dimensional mesh structure - the design and simulation of the process of the Resource Network Interface (RNI) and switch (switch) . Of hardware description language (HDL) Verilog register transfer level (RTL) code to write , and the preparation of the test platform , simulation Modelsim simulation software of its functions . The simulation results show that : The design the RNI and switch logic function properly .

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Microelectronics, integrated circuit (IC) > LSI,ultra LSI
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