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The design of low - voltage, low -power 10 -bit 40 MHz pipelined ADC

Author: GuoYao
Tutor: RenJunYan
School: Fudan University
Course: Microelectronics and Solid State Electronics
Keywords: ADC pipeline sample-and-hold circuit operational amplifier sharing two-stage amplifier
CLC: TN792
Type: Master's thesis
Year: 2009
Downloads: 241
Quote: 2
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Abstract


As the interface circuit of the analog signal and the digital signal, analog-to-digital converter has been widely used in the base station、receiving system of the satellite、medical instrument、radar、digital oscillograph and consumer electronics.First it has been driven by the market of consumer electronics;the widely used portable facilities powered by battery require the high resolution high speed analog-to-digital converter with low power.At the same time,with the development of the integrated circuit process,the power supply is decreasing,so the design with the low power supply is also very important.The pipelined analog-to-digital converter has become the most popular architecture among all the kinds of the A/D converters.Based on the analysis of the principle and structure、the non-ideal factor of the pipelined A/D converter and the techniques to reduce the power both at system level and circuit level,a 10-bit 1.2V 40MHz pipelined A/D converter is presented in this thesis.The A/D converter is implemented with 1.5bit/stage pipelined structure,with front-end sample circuit to ensure the performance when the frequency of the input signal is higher than the Nyquist frequency.A two-stage amplifier is used to achieve the high-gain、high-bandwidth and high-swing with the low power supply.The first stage is folded cascode structure and the second stage is the source-follow structure, cascode compensation is used to reduce the power.To reduce the power consumption, the operational amplifier sharing technique,along with the capacitor scaling down and using of dynamic comparator techniques is used.This A/D converter is fabricated in SMIC 0.13μm,1P8M mixed-signal CMOS process,and the power supply is 1.2V.This chip occupies an area of 1.76×1.04mm~2, consuming only 15mW.The ADC achieved a signal-to-noise-and-distortion ratio (SNDR) of 60.8dB,SFDR of 76.8dB for an input of 19MHz when the sampling clock is 40MHz in SS corner.And with an input of 39MHz,the ADC achieved SNDR of 59.8dB,and SFDR of 74dB.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Basic electronic circuits > Digital circuits > Digital-analog , digital to analog conversion circuit
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