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Design and FPGA Implementation of Improved RS Codec Algorithm in Digital TV Systems
Author: KongDeChao
Tutor: LiuZhiJun
School: Shandong University
Course: Circuits and Systems
Keywords: Wired Digital Video Broadcasting Galois field multiplier RS code Field Programmable Gate Array Quadrature Amplitude Modulation
CLC: TN949.197
Type: Master's thesis
Year: 2009
Downloads: 163
Quote: 3
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Abstract
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China 's digital TV industry through the Beijing Olympics in the east, has been rapid development . This topic is derived from the national digital television standard DVB-C QAM modulator items. RS (Reed-Solomon) code is the error control field an important class of linear block codes . Since the RS code has both a random error and burst error correcting ability to correct burst errors and more efficient , which is widely used in various error control schemes . National digital television standard DVB-C QAM modulator using the RS (204,188) code . In this paper, a new field multiplier constant coefficients Galle China , completed the design of a kind of high-speed, low-complexity characteristics of RS coding algorithm , the algorithm can reduce the logic unit , reducing system overhead , and easily ported to other RS code length encoding . By downloading to Xilinx's Spartan-3E family of devices hardware testing , to verify the design features and gives the correct waveform . To facilitate follow- QAM demodulator related work, the paper also designed a BM iterative algorithm based on RS decoder by FPGA. This completed work are: 1 . Introduces the mathematical basis of RS coding , completed the RS coding theory mathematical derivation . 2 shows the RS encoding core device Galois field multiplier conventional design. 3 presents a new Galois field multiplier and combine it to complete the improved algorithm RS encoder design, which simplifies the hardware , reducing system overhead. And adopted the timing simulation and hardware verification . 4 introduces the BM iterative algorithm, design iterative algorithm based on BM by RS decoder FPGA, through the functional simulation , has been RTL circuit.
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CLC: > Industrial Technology > Radio electronics, telecommunications technology > TV > TV : Press the institutional sub- > Digital TV
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