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Design and Implementation of Parallel MPEG-4 Decoder Based on Multi-core DSP

Author: HuangYongHong
Tutor: XuBangJian
School: National University of Defense Science and Technology
Course: Software Engineering
Keywords: Multicore DSP MPEG-4 Parallel decoding Macro water Data -level parallelism
CLC: TN764
Type: Master's thesis
Year: 2009
Downloads: 162
Quote: 1
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Abstract


With the emergence of the MPEG-2 standard , digital television, Internet streaming and DVD can be widely applied . The video compression technology to become a key part of the communications , broadcasting and entertainment multimedia . MPEG-4 is a generation after the MPEG-2 compression standard object-based multimedia information codec . MPEG-4 is due to the high computational complexity , making it difficult to achieve the requirements of the real codec in a digital signal processor , based on the MPEG-4 of the multicore processors, parallel to become a research hotspot . Of Computer Science , National University of Defense Technology independent research and development of a multi-core digital signal processor (MDSP), Based MDSP Design and Implementation of the MPEG-4 parallel decoder . This article studies the MDSP architecture and characteristics of MPEG-4 video algorithms , the eventual realization of a parallel implementation of the MPEG-4 decoder on a 4-core DSP . The main work and results are: 1, to analyze the MDSP the system structure , focusing on the inter-core communication and synchronization , and design to the completion of the inter-core communication and synchronization library functions ; research MPEG-4 video codec algorithm standard analysis of MPEG- 4 decoder algorithm in the presence of correlation, and the decoder of each main module computational complexity analysis; 3, based on the parallel analysis of the MPEG-4 decoder , the data level of the two macro pipelining and 3 nuclear the parallel combination of parallel decoder implementation ; 4, two communication modes use SDP and the SDP and QLink mixed parallel MPEG-4 decoder in the MDSP . Run parallel decoder in RTL (Register Transfer Level) level , analysis of the experimental results ; 5 , on the basis of the analysis of the experimental results , according to the characteristics of the algorithm , the of MDSP communication module proposed a few improvements .

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Basic electronic circuits > Modulation technique and the modulator,demodulator and the demodulator > Decoder
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