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The Design and Implementation of 12 Bits 400MSPS Digital-to-Analog Converter in 0.18μm CMOS Technology

Author: ShiDaYong
Tutor: ChenNuXing
School: National University of Defense Science and Technology
Course: Software Engineering
Keywords: DAC Current-Steering Matching Error Bandgap Reference
CLC: TN792
Type: Master's thesis
Year: 2009
Downloads: 193
Quote: 2
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Abstract


Nowadays, digital to analog converter (DAC) plays a very important role in the modern digital and analog circuit, and it is also a key to improve speed and precision of signal process. It is a main factor that restricts the development of the computer, communication and DSP. In the near years, high-speed high-resolution and embedded DAC have been widely studied in abroad, but both fall behind in our country.In this paper, a 12bit 400MSPS segmented Current-Steering DAC is designed with 1.8V single power supply under 0.18μm CMOS logic technology, and the full rang of output current is 20mA.Firstly, based on the chip area, complexity and the performance of the circuit, the design adopted 5+4+3 segmented Current-Steering structure to achieve the optimal combination of unit current source and binary weighted current source. The paper also set up a nonideal model based on MATLAB to analyse the error which is caused by current mismatch, finite output impedance of the current source simply and quickly, it can be used to guiding DAC design optimally.In the circuit design of DAC, paper made full use of the method based on circuit structure optimization to restrain the influence of the nonideal factors combined with the model analysis of the DAC. Furthermore, a high performance bandgap reference circuit is designed in this paper to provide stable voltage for the DAC, so the current source can produces stable current, which is insensitive to technology and temperature.In the layout placement, paper presented a hybrid placement strategy to reduce the area as well as the errors of the DAC in combination with the excellences of the symmetry center and Q~2 Random walk switching scheme.the result of post-simulation shows that the DAC has good monotony, the DNL and INL are both±0.75LSB, SFDR=70dB@fs=400MSPS, fout=10MHz, and the average power is 114mW.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Basic electronic circuits > Digital circuits > Digital-analog , digital to analog conversion circuit
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