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Research of Design Techniques for Reconfigurable Arithmetic Unit in Galois Field

Author: QinFan
Tutor: DaiZiBin
School: PLA Information Engineering University
Course: Military Communication
Keywords: Elliptic Curve Cryptography Finite field Montgomery multiplication Montgomery inverse Configurable structure
CLC: TP332.2
Type: Master's thesis
Year: 2009
Downloads: 54
Quote: 3
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Abstract


Papers according to the needs of current ECC password arithmetic processing to design configurable ECC chip target unit can be configured to support any parameter of the ECC dual finite field operations over finite field research : papers on finite field arithmetic algorithms, including finite field addition and subtraction algorithm, finite field multiplication algorithm and finite field inversion algorithm research . From the complexity of the algorithm , the operation cycle , the hardware implementation of these three areas , based on mainly limited domain algorithm to analyze and compare , the paper presents optimized hardware implementation of large integer modular addition and subtraction algorithm ; choose FIOS Montgomery modular multiplication algorithm design finite field multiplication unit and the type of BLWL FIOS algorithm optimization simplify the algorithm middle of the process operator to reduce the critical data path delay : four support a number of different domain conversion algorithm for Montgomery modular inversion algorithms design , to further improve Find the inverse operation gamut conversion efficiency and flexibility . Papers hardware implementations of the algorithm to optimize the design , the proposed the hardware circuit structure can be configured to support two different finite field operations, and support the operation of the variable-length data . To improve the hardware operation speed of the circuit and the clock frequency to optimize the design of the circuit data path , comprising: a rapid design of the adder and subtractor unit , to reduce the data path delay ; optimize the modular multiplication pipeline org , shortening the calculation cycle . Thesis algorithms and hardware circuit design , circuit simulation and testing . RTL-level code description Verilog hardware description language to complete the circuit to Altera Corporation Quartus7.2 software simulation, and downloaded to the FPGA development board for hardware verification . For ASIC implementation performance parameters , the synthesis tool DesignCompiler in Synopsys' under the integrated circuit synthesis and simulation library of standard cells using SMIC 0.18μm CMOS technology library . Consolidated results show that , compared to other configurable design , this paper finite field arithmetic unit can be configured to have greater advantages in speed of operation , the circuit clock frequency and area .

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CLC: > Industrial Technology > Automation technology,computer technology > Computing technology,computer technology > Electronic digital computer (not a continuous role in computer ) > Arithmetic unit and the controller (CPU) > Arithmetic unit
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