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Convolutional Turbo coding performed by FPGA implementation

Author: GaoZiWang
Tutor: GuMeiKang
School: Shanghai Normal University
Course: Communication and Information System
Keywords: CTC FPGA MAP Max-log-MAP Latency
CLC: TN791
Type: Master's thesis
Year: 2010
Downloads: 129
Quote: 1
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Abstract


Convolutional Turbo Code has attracted more and more attention due to its excellent error correction performance, where the encoder and decoder are the emphasis and difficulty of the practical application of coding theory.According to standard IEEE802.16e,the paper deals with the implementation of Convolutional Turbo Code encoder and decoder with FPGA,aimed at low latency, high throughput, high clock frequency supported and parameter configuration supported.The paper introduces the principles of Convolutional Turbo Code encoding and then designs the encoder in detail by using top-down principle. Sequence interleaver and sub-block interleaver are not only essential components of the encoder but also the bottleneck for improving the clock frequency. The paper adopts look-up table-based approach to implement interleavers, which provides several advantages such as low complexity, generability, low latency and short critical path. It also divides the memory space of interleaver reasonably to minimize the consumption of embedded RAM, on the premise that the highest clock frequency is guaranteed. In addition, the paper contains a detailed and reasonable design of encoder process, in order to reduce the encoder latency and improve throughput.Similarly, before the decoder design, there is an introduction of decoding principles and a detailed derivation of MAP and Max-Log-MAP decoding algorithm, mainly including the calculation of branch metrics, forward state metrics, backward state metrics, external information and log-likelihood ratio.Analysis of Convolutional Turbo Code decoder shows that alike the traditional turbo decoder, the critical path of Convolutional Turbo Code decoder exists in the forward/backward state metric calculation unit, which is composed of the adder, comparator, selector and normalization logical link. However,there are not two inputs but four inputs to comparator and selector. This is the reason why the highest clock frequency of the CTC decoder is lower than one of conventional turbo decoder. The paper specially designs the comparator and abandons the normalization for state metric, for the purpose of reducing the critical path. In order to reduce the decoder latency and improve the throughout, the following measures are adopted.Firstly,adopt pipeline technique, dividing the decoding process into data de-multiplexing, decoding iteration and data output. Decoding iteration can be continuously carried out without waiting for data de-multiplexing or data output. Secondly,adjust the sub-decoding sequence. DEC2 go ahead of DEC1. it saves time,because there is no need to de-interleave the log-likelihood ratio of information bits when judge the information bits. Finally,calculate the forward state metrics and backward state metrics at the same time. By calculating the external information in advance, it reduces the decoding latency ,without sacrificing the decoding performance.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Basic electronic circuits > Digital circuits > Logic circuits
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