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Research and design of the FFT processor multiplier multiplexed multiplexer

Author: WangWenYi
Tutor: ZhouXiaoFang
School: Fudan University
Course: Microelectronics and Solid State Electronics
Keywords: FFT Assembly line SDF Base LTE Multiplexer Constant coefficient multiplier
CLC: TN919.3
Type: Master's thesis
Year: 2011
Downloads: 94
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Abstract

With the rapid development of microelectronics technology, complex digital signal processing technology is being used in various fields, especially in the communication technology is widely applied FFT algorithm has become an integral part of communication. In recent years, communication technology for high-speed and real-time requirements getting higher and higher, in order to meet the growing communication needs of the communication port, OFDM and MIMO convergence trend is the general trend OFDM technology can improve the spectrum efficiency, MIMO technology can be multiplied improve the system capacity. Due to the fusion of the two, the research on the FFT by the single-channel FFT configurable multi-channel FFT direction of development of many communication protocols have been applied to the configurable multi-channel FFT, such as LTE protocol. FFT processor detailed study of the current algorithms and architectures. Researchers for the study of the FFT algorithm has been very mature, very difficult to make a breakthrough, so this article is to study from the perspective of architecture and implementation FFT processor. In this paper, Algorithm FFT processor architecture features, focusing on the pipeline structure: MDC and SDF structure. To SDF in order to meet the application requirements of the low area, as a basic structure and optimized design the two low area of ??multi-channel FFT processor architecture, referred to as the structure A and structure B. Structure A-24-based algorithm, structure B based-8-16 algorithm, although the algorithm is different, but they are often multi-channel FFT processor coefficient multiplier reuse data flow control strategy to improve the multiplier use rate, reduce the use of the multiplier to achieve a reduction in area of ??effect and power consumption. The text of the structure A and structure B, as well as other typical structure. This article selection structure B for the basic structure of the LTE can be configured in the FFT processor has been designed, based on the LTE protocol, select the appropriate algorithm. FFT processor can be configured in the specific design of LTE, the overall design is divided into two parts of the data flow and control flow, is conducive to implementing and debugging data stream work at 30.72MHz, the main memory part of the work in the 122.88 MHz synchronous clock frequency. In order to ensure the functionality and reduce the area as the target to reasonably split merged memory, and select the appropriate type of RAM, improve the utilization of the RAM, the multiplexed with the RAM and reduce the chip area of ??the. The twiddle factor is 1/8 domain rotation factor to improve the efficiency and reduce the use of the ROM. The final design of the the low LTE plot the FFT processor can be configured, and the processor having a good configuration, not only based on the LTE protocol to select the appropriate length of the FFT, and also from the perspective of signal-to-noise ratio and power dissipation to the outside the configurability. Finally, build FPGA test platform can be configured on the design of the LTE FFT processor implementation, verification and testing, the ultimate realization of FFT processor in the Xilinx development board test.

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