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Wet etching the sacrificial oxide layer on the gate oxide layer of impact

Author: DingShiCheng
Tutor: LiBingZong；LuoShiZhou
School: Fudan University
Course: IC Engineering
Keywords: Sacrificial Oxide Wet Etching Gate Oxide
CLC: TN405
Type: Master's thesis
Year: 2011
Downloads: 36
Quote: 0
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Abstract


The importance of clean substrate surfaces in the fabrication of semiconductor microelectronic devices has been recognized since the early days of the 1950s. As the requirements for increased device performance and reliability have become more stringent in the era of VLSI and ULSI silicon circuit technology, techniques to avoid contamination and processes to generate very clean wafer surfaces have become critically important. Besides, over 50% of yield losses in integrated circuit fabrication are generally accepted to be due to micro-contamination.Many wafer cleaning techniques have been tested and several are being used. The generally most successful approach for silicon wafers without metallization uses wet chemical treatments. This process has remained essentially unchanged during the past several decades and is developed base on hot alkaline and acidic hydrogen peroxide solutions, a process known as "RCA Standard Clean," which was developed at RCA, introduced to device production in 1965, and published in 1970.Impurities on silicon wafer surfaces occur in essentially three forms: (i) contaminant films, (ii) discrete particles, and (iii) adsorbed gases that are of little practical consequence in wafer processing. But, the purity of wafer surfaces is not the only requirement any more, the surface state and micro-roughness after cleaning treatment become quite important for the successful fabrication of ULSI silicon circuits.It is revealed that the ratio of over etch for sacrificial oxide has the determining influence on the surface state during the processing of gate oxide pre-cleaning. At 0.13um technology node, the ratio of over etch for sacrificial oxide must be decreased for the concern of divot at the corner of active area. But too low ratio of over etch will result in the insufficient termination of hydrogen. In this case, the variation of etching rate of dilute HF will bring much higher fluctuation on the following gate oxide growth, then the electrical performance of device, the final production yield.This article studies the process window of the over etching ratio for the sacrificial oxide during gate oxide pre-cleaning process and works out the best solution under the consideration of both the divot concern and the sufficient hydrogen termination base on 0.13um CMOS (Complementary Metal Oxide Semiconductor) technology. After the best solution implementation, it brings the great reduction of engineering loading, the remarkable improvement of tool efficiency and process precision capability and yield gain.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Microelectronics, integrated circuit (IC) > General issues > Manufacturing process
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