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Evolvable Hardware Platform

Author: YangHuaQiu
Tutor: LaiJinMei
School: Fudan University
Course: Microelectronics and Solid State Electronics
Keywords: Evolvable hardware LUT -level evolution Module-level evolution Chip-level evolution Network-level evolution
CLC: TN47
Type: Master's thesis
Year: 2011
Downloads: 85
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Abstract


Evolvable hardware (EHWW) can simulate the process of biological evolution, under the guidance of the evolutionary algorithm for self-reconfigurable and close to the target function, the circuit design, adaptive systems and other fields have a wide range of applications. EHW technology, while after nearly two decades of development, but in how the application needs to provide hierarchical research platform for individuals to effectively assess and improve the speed of evolution, there are still a large scale exploration of space. Based on independent research group FPGA technology, attention to different levels of granularity evolvable hardware platform on reconfigurable technology, evolutionary algorithms and evaluation strategy needs to study the LUT (Look Up Table) level, module level, chip-level and network level four kinds of evolvable hardware platform. First, based on independent research and development research group established a LUT FPGA chip-level evolvable hardware platform, this platform has developed an evolutionary algorithm prevents evolutionary stagnation; designed LUT-level reconfigurable circuit, the unification of combinational logic and sequential logic the evolution of the process and provides adaptive assessment algorithm to evaluate the circuit. Experimental results show that this platform has been reported in more than similar platforms evolve faster than tenfold. Then, based on self-FPGA chip, and further study of the module-level evolvable hardware platform, focusing on its core needs: module-level part of the dynamic reconfigurable hardware. This innovative design of a transmission line based on longitudinal CLB macro provides the appropriate tool chain, and the development of some of the dynamic reconfigurable image filter demonstration system. Experiments show that the demonstration system hardware circuit can be completed within 50 milliseconds module-level reconstruction, adaptation module level evolvable hardware platform core needs. Furthermore, in order to further improve the speed of evolution of a chip-level hardware platform can evolve. This platform independent design integrates a CPU core and FPGA programmable chip as the main nucleus. In chip design, the development of a rapid reconstruction configuration technology, can significantly reduce the time required for refactoring operations; provides solutions for different fitness evaluation data exchange interfaces, improve system reliability and flexibility; through hardware acceleration methods to achieve the genetic algorithm acceleration. This platform evolution experimental results show that the speed of evolution than the examples in the literature an order of magnitude faster. Finally, in order to provide a more efficient module-level evolutionary program that will own FPGA technology and network on chip (NOC) technology, studied a network-level hardware platform can evolve its core is a kind of multi-FPGA core network node The NOC reconfigurable chip, through the on-chip routers and network resource interface for innovative design, make this platform supports network-level network architecture and network node reconfiguration reconfigurable two characteristics. Simulation and FPGA verification results show that this platform prototype function properly, and support per node per period per point injection 0.7 data to the network.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Microelectronics, integrated circuit (IC) > LSI,ultra LSI
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