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Reed-Solomon decoder implementation study

Author: HuangBei
Tutor: ZengXiaoYang；YuZhiYi
School: Fudan University
Course: Microelectronics and Solid State Electronics
Keywords: Reed-Solomon Decoder CMMB multi-mode multi-core processor mapping strategy
CLC: TN762
Type: Master's thesis
Year: 2011
Downloads: 25
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Abstract


Research for the implementations of a Reed-Solomon Decoder is the main purpose of this thesis. ASIC is the common solution for most digital communication baseband. The requirements about power consumption and chip area can be satisfied by carefully design of the hardware architecture. In hence, the evolution of hardware architecture of RS decoder never stops during the last decades. However, ASICs has their imperfection:long developing period, high cost of tape-out and so on. Solutions with low cost and short developing period are under research by many researchers and companies. And all these researches show that software solution on a appropriate platform is a better choice.According to the background and discuss above, in this thesis, two implementations are proposed, one is ASIC implementation of multi-mode RS decoder in CMMB, the other is software implementation of a high throughput RS decoder on multi-core processor platform. In the first half of this thesis, we designed a multi-mode architecture for RS decoder in CMMB which is very area efficient and low power consumption. The chip test result shows it can work at a very high clock frequency, and have some advangtage on area and power consumption compared with other similar works. And in the second half of this thesis, we in-depth analysis the decoding algorithm of RS code for the possibility of parallelism computing which include pipeline parallelism, task parallelism and data parallelism. And then according the fetures of decoding algorithm, map the whole decoding algorithm onto multi-core platform. Simulation results shows, it can achieve a very high throughput and better performance compared with other works.With the experience of the two implementations, we analysis the advantages and disadvantages for these two solutions of communication applications:ASIC implementation and software implementation on high performance processor.When working with the RS decoder on multi-core processor, due to lack of tools, we experienced with a very hard time of debugging the program. So we research and development core-level debug probes through the EDA tools’interfaces and a systemlevel debug agent; expected to facilitate the programers to identify bugs in Multi-Core based systems more effectively and efficiently.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Basic electronic circuits > Modulation technique and the modulator,demodulator and the demodulator > Encoder
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