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FPGA chip TILE unit modeling and fault coverage analysis

Author: XuWenFeng
Tutor: LaiJinMeiï¼›GuoYaZuo
School: Fudan University
Course: IC Engineering
Keywords: FPGA Modeling Fault coverage TurboFault
CLC: TN402
Type: Master's thesis
Year: 2011
Downloads: 44
Quote: 0
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Abstract


FPGA is currently widely used as a programmable logic device FPGA appear to fill the defects of ASIC design costs, design cycle . FPGA is divided into three parts: the structure of logical resources , the structure of interconnection resources and programming configuration . FPGA chip logic resources , the basic unit of Internet resources TILE modeling , design the TILE basic unit functional simulation model, and completed the the TILE - cell interconnect model simplify the design process and the functional unit programmed point configuration process to complete TILE unit functional simulation and verification. Additionally, this article software TurboFault , a set of traversal test pattern designed on the the SLICE unit configured for the TILE unit responsible for the logic functions of the fault coverage testing . Eventually, we got fault coverage report for each test pattern , and overall fault coverage analysis of finishing the test pattern fault coverage report , found some of the original fault not covered , and through the design of a new test pattern the fault coverage . In order to better accomplish the of TILE unit modeling , simulation , this paper put forward in the design process the logic resource module modeling ideas and on interconnect module simplifies modeling an innovative approach , and for TILE cell simulation process the functional units in programming point configuration design solutions for a creation of a programming point of configuration information from the configuration file . Final paper design the script to complete these procedures , the configuration file from the test pattern TILE unit functional simulation model and programming point configuration file , not only to help complete the test pattern fault coverage testing , but also for the whole FPGA chip the realization of the functional simulation software and method . Final , after an analysis of the existing test pattern , summed up the a TILE unit as two slice units in the case of the simulation test model does not cover failures and reason , and for the single SLICE unit supplement designed a new test pattern , the the SLICE unit test pattern fault coverage increased to 93.4 % , through the data quantitatively assess the validity of the test pattern .

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Microelectronics, integrated circuit (IC) > General issues > Design
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