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The Design of High Speed a Low Jitter Fully Differential CMOS Phase Locked Loop

Author: HeRuiTao
Tutor: YuZhongChen
School: Beijing University of Technology
Course: Microelectronics and Solid State Electronics
Keywords: Phase-locked loop High speed Charge Pump Fully differential loop filter
CLC: TN432
Type: Master's thesis
Year: 2010
Downloads: 150
Quote: 1
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Abstract


PLL frequency synthesizer is now increasingly widely used in communications , microprocessor systems , and with the development of integrated circuits as well as the emergence of the SOC technology , has become an integral part of VLSI module . Especially in the field of wireless communications , high-speed processor , the increasing demands on the performance of the PLL circuit , PLL circuit has become a challenge working in a high-speed environment . In this paper, a survey of the history and current status of the development of phase-locked technology based on phase-locked system works , analyzes the mathematical model of a phase-locked loop . Subsequent analysis of the phase-locked loop stability , dynamic characteristics and noise characteristics , derived the principle of the system loop parameters , the theoretical basis for the subsequent circuit design and layout . Then analyze the advantages and disadvantages of traditional circuit on the circuit structure , and a new circuit structure . Mainly using new PFD circuit structure , this structure to avoid the phenomenon of clock edge and increase the delay time of the reset control signal to eliminate the dead zone effect brought lost ; the use of a new charge pump structure , with a resistor in place of the conventional MOS tube , eliminate the the flicker noise impact ; fully differential regulator instead of the traditional single-ended regulator, further reducing the impact of power supply noise on the VCO ; using high-speed the DFF and low-speed DFF phase as the way to achieve the counter . Phase-locked loop using SMIC 0.13 ? M 1P8M ( single to polysilicon eight-story metal ) , 1.2V mixed-signal CMOS technology , the chip area is 400? M * 400 ? M . Input reference frequency of 25MHz, the output frequency of 2.5GHz , the lock time of less than ? S, the power consumption of 25mW , former imitation RMS Jitter approximately 7.4 ps .

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Microelectronics, integrated circuit (IC) > Semiconductor integrated circuits ( solid state circuits ) > Field-effect type
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