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Design of Video Acquisition System Based on NiosⅡ

Author: ChenZhiXing
Tutor: ZhangSuWen
School: Wuhan University of Technology
Course: Control Science and Engineering
Keywords: Nios II Video Capture FPGA IP core
CLC: TP274.2
Type: Master's thesis
Year: 2010
Downloads: 329
Quote: 8
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Abstract


With the computer, networking and communications technology, the rapid development of digital image and video technology has been widely used in security monitoring, industrial inspection, consumer electronics and intelligent transportation and other fields. And how to achieve high-speed digital image acquisition is a key technology of digital image processing. This article is designed based on Nios Ⅱ processor video image acquisition system, which in Nios Ⅱ processor core, combined with a wealth of IP cores in a single FPGA chip to achieve a high-speed video capture and display capabilities. Firstly, analysis and comparison of existing programs, and then presents the design of this system, focusing on analysis of the video image acquisition system's overall architecture and its realization principle. Brief description of the various components of the system and the system design requirements of the chip selection. Next, CMOS controller and LCD controller is designed to do a detailed exposition. CMOS controller controls the camera to complete the image acquisition and processing; sends the processed data into the SDRAM. For this module, first using Verilog language I2C bus timing simulation in order to achieve the initial configuration of the camera, and then control the camera capture image data. Then the collected data obtained by the color space conversion for subsequent LCD display. To improve the image display quality, the converted image data of the median filtering process. Finally, add the Avalon Interface CMOS controller IP core to complete the package. LCD controller function is achieved by driving the LCD screen to display the captured images. For this module, mainly to complete the preparation of the timing control module, DMA controller will read the data in SDRAM FIFO buffer, and then through the timing control block data in the FIFO and then displayed on the LCD readout hydrazine. After the completion of each module design in SOPC Builder environment for the required IP core can be configured to get the system top circuit. Subsequently, in the Nios Ⅱ IDE environment using C Wu Yan completed the system software design and debugging, including the system driver development and system application development in two parts. Drivers and underlying hardware directly dealing with the macro definition, Nios Ⅱ processor through the driver for the controller to operate. For system applications, this paper uses a synchronous design in order to avoid both CMOS and LCD interfaces generated when accessing SDRAM read and write conflicts. This design gives the LCD interface transfer priority DMA transfer only when the end of the LCD CMOS DMA transfer can begin. Finally, the text of a summary and outlook, raised the need to further improve and perfect place.

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CLC: > Industrial Technology > Automation technology,computer technology > Automation technology and equipment > Automation systems > Data processing, data processing system > Data collection and processing systems
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