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Low Power Design in 10 Bit CMOS Pipliened ADC

Author: HuoZeng
Tutor: DuanMuQingZuo;YuZhongChen
School: Changchun University of Science and Technology
Course: Microelectronics and Solid State Electronics
Keywords: Pipelined analog - to - digital converter Complementary Metal Oxide Low power consumption
CLC: TN792
Type: Master's thesis
Year: 2008
Downloads: 171
Quote: 0
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Abstract


The integrated circuit has entered the stage of system-on- chip (SOC) . Communications, video processing , such as mixed-signal system , high-speed , low-power ADC is a crucial part . Compared with other structural characteristics of the pipeline (PipelinedArchitecture) ADC structure to achieve both high-speed and can achieve very high resolution . This design uses 0.18μm 1P6M CMOS mixed-signal production technology, 10-bit conversion accuracy , the conversion rate for the 40 MHz A / D converter . First pipelined analog - to - digital converter circuit made ??the introduction of the system , and theoretical analysis of the power consumption of the ADC suppression technology , from the structure to the low power consumption of the circuit pipelined ADC design methods and standards : 1 . SHA-Less design , reduce the number of stages of the ADC . 2 . Choose the best single-stage resolution and capacitive progressively decreasing , thereby reducing power consumption . 3 circuit core module of the op amp and comparator power optimization design . Finally, Cadence Design software to complete the 10 - bit pipelined ADC circuit design , Semiconductor Manufacturing International (SMIC) 0.18μm 1P6M CMOS model layout simulations . In the final chip testing results , the input signal is 9 MHz, sampling frequency of 40 MHz , the conversion accuracy can reach 8.7 bit effective number of bits , to meet system requirements . Power consumption of 48 mW under 1.8 V power supply voltage .

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Basic electronic circuits > Digital circuits > Digital-analog , digital to analog conversion circuit
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