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Standard digital CMOS process high speed pipelined ADC Research and Design

Author: ShengYun
Tutor: HongZhiLiang
School: Fudan University
Course: Microelectronics and Solid State Electronics
Keywords: Pipelined ADC Digital CMOS process Noise model Symmetrical gate voltage bootstrap switch Adaptive switch substrate
CLC: TN792
Type: Master's thesis
Year: 2008
Downloads: 257
Quote: 0
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Abstract


Consumer electronics products in the market of digital cameras, digital televisions, monitors and projectors and other video applications widely used to promote the rapid development of video processing circuit . As a bottleneck module , high-speed precision ADC has become a hot research topic. This paper studies the standard digital CMOS technology for system integration , low-cost high-speed high-precision pipelined ADC (ADC) is achieved. In the system design , this paper through the establishment of switched-capacitor pipeline ADC noise model , the median level and get the optimal value of the sample and hold capacitor ; according to the established level circuit op amp current error model is optimized. Concluded a high-speed low-power pipeline ADC design flow . Devices to achieve , and explore the standard digital CMOS technology to achieve high capacitance , we propose two practical metal interconnect line capacitance : capacitance per unit area with a high rate of staggered metal interdigital capacitor and has good matching characteristics of metal plate interdigital capacitor. Finally , the design of a front-end for video 10 110MS / s pipelined ADC, and completed a flow sheet and tested. The ADC uses 0.18μm standard digital CMOS process , the power supply voltage is 3.3/1.8V, integrated wideband variable gain sample and hold circuit and on-chip reference source . The paper also uses the symmetric bootstrap switch gate voltage , the substrate adaptive switch , common tube and a tube with thick gate of the OTA and other design techniques to achieve the highest sampling frequency of 110MHz . Test results show that , DNL and INL are less than 1LSB and 2.7LSB, the sampling frequency and the input frequency of 100MHz and 5.1MHz , respectively, when SFDR is 58.5dB, SNDR is 48.7dB. When the sampling frequency and the input frequency is 14.7MHz and 6.9MHz , respectively, when , SNDR is 58.7dB. ADC consumes 190mW, an area of ??2.7mm ~ 2.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Basic electronic circuits > Digital circuits > Digital-analog , digital to analog conversion circuit
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