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FPGA interconnect structure and layout algorithm

Author: Tan
Tutor: WangLingLi
School: Fudan University
Course: Microelectronics and Solid State Electronics
Keywords: FPGA Routability Delay The switch boxes hierarchical model Universal wiring block
CLC: TN791
Type: Master's thesis
Year: 2008
Downloads: 357
Quote: 3
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Abstract

Field-programmable gate array (FPGA, Field Programmable Gate Array) due to programming, debugging, and then repeat the operation programming, and can fully develop verification is considered to be the fastest way to build a semiconductor chip design prototype than dedicated integrated circuit (ASIC, Application-specificintegrated circuit) environment faster compatible design, and lower risk. Closely related to a variety of different sized circuit implemented in FPGA routability and performance FPGA architecture. With the increasing scale of integrated circuit design, FPGA in order to meet the needs of this design, the scale is bigger and bigger, the traditional structure of the FPGA is unable to meet the demand for the actual design, poses a great challenge in the design of hardware structure, but also proposed new requirements for computer software, and a variety of complex problems are concentrated to the placement and routing (PR) of this step to improve the various circuits in the FPGA fabric through rate, reduce delay. So, how to design a generic placement and routing tools to seek more optimized FPGA hardware structure, how to improve the placement and routing algorithms to achieve efficient use of existing FPGA architecture exploration direction. FPGA's basic components include: a programmable logic unit, the input-output unit, and programmable interconnect resources [1]. Wherein the interconnect lines, the switch box (SB, Switch Box) and the connection box (CB, Connection Box) is composed of a main portion of the the FPGA programmable interconnect structure. For the specific FPGA architecture, the rational use of the the wiring resources already in the FPGA logic cell array and channel, circuit functionality and improve performance, layout target. In traditional island FPGA architecture universal switch boxes hierarchical model, the inner layer of the model can be used to describe any of the four sides of the switch box structure. On the basis of this model, this paper proposes a new switch box structure JSB has been greatly improved routability than three classic switch box; In addition, through the establishment of the outer layer of the switch box model, flexible distribution within the FPGA crossbar channel programmable interconnect lines, increasing the possibility of connection between the heterogeneous interconnect channel, this paper presents an optimization strategy to optimize circuit delay. Commercial FPGA merge traditional switch box and connection box, universal wiring block (GRB academic General Routing Block) programmable interconnect structure GRB structure fast connection between the pin and the tube feet with different channel interconnect cable to a certain area of ??the cost, greatly improve routability and delay. Practical FPGA research, independent research and development FPGA chip FDP250K of design with the layout of the clock, bus, macro module layout algorithm to take advantage of a variety of FPGA logic resources, and supports a variety of circuit in FDP250K chip Application.

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