Dissertation > Excellent graduate degree dissertation topics show

Design of a Fully Differential 1GHz CMOS PLL Frequency Synthesizer

Author: ChenMingYi
Tutor: MaoLuHong
School: Tianjin University
Course: Microelectronics and Solid State Electronics
Keywords: Phase Locked Loop frequency synthesizer phase noise spurious tones wireless RF receiver CMOS
CLC: TN911.8
Type: Master's thesis
Year: 2007
Downloads: 228
Quote: 0
Read: Download Dissertation

Abstract


A Phase Locked Loop (PLL) RF frequency synthesizer with 1GHz output frequency has been designed based on Singapore, Chart0.35μmEE library and 3.3V supply voltage in this paper. Wide loop bandwidth (7MHz) has been used to suppress the phase noise from the Voltage Controlled Oscillator (VCO).The fully differential topology has been adopted to suppress the common mode noise such as the power supply noise, the substrate noise and the environment noise.The whole flow of RF front end design—from the system level to the circuit level has been done. In the system level design, the loop bandwidth has been optimized and the behavior level simulation in time domain has been done using the Simulink tool of Matlab, while in the circuit level design, all the essential blocks have been designed and the whole circuit has been simulated using Cadence Spectre RF.The simulation results show that the output frequency can be locked to 1GHz in ss, typical and ff corners while the settling time is less than 500ns. The phase noise at 500 kHz frequency offset is -103dBc/Hz,-105dBc/Hz,-102dBc/Hz while the spurious tones at 100 MHz are -43.9dBc, -42.6 dBc,-47.2dBc in three corners, separately. When a 25MHz,100mV peak to peak sine wave is added to the supply of all the blocks except the VCO, the output frequency is still 1GHz and the spurious tones at 100MHz is nearly unaffected, while the spurious tones at 25MHz are -48dBc, -48.7 dBc,-51dBc in three corners, separately. The simulation results show that the designed PLL frequency synthesizer meets the design specification and it can be used in the integrated wideband IF with double conversion wireless RF receiver.

Related Dissertations

  1. Application of FPGA in Low SVG,TN791
  2. The Application of CMOS Imaging Sensor on AOI Equipment,TP212
  3. Charge-Pump PLL Z-domain Analysis and Low Noise Design,TN911.8
  4. Research and Design for CDR in Ultra High-speed Optical Fiber Communication Systems,TN929.11
  5. The Research and Design of Radio Frequency Monolithic Voltage Controlled Oscillator in 0.18μm CMOS Technology,TN752
  6. The Design and Research of 4GHz DRO with Low Phase Noise,TN752
  7. X-band low phase noise PDRO Design and Implementation,TN752
  8. Millimeter-wave radar frequency step frequency synthesizer design,TN958
  9. Shortwave radio frequency source synchronous design and research,TN74
  10. DBF microwave system design and implementation phase locked source,TN911.8
  11. Fractional-N frequency synthesizer Modeling and Design,TN74
  12. Applied GPS/BD2 quadrature receiver VCO design,TN752
  13. Ku-band linear FM detector RF front-end technology,TN911.3
  14. Ethernet Controller Physical Layer Clock Recovery Circuit Design,TP273
  15. Development of a C-Band Transceiver,TN859
  16. Research on Phase Noise Suppression in OFDM Systems,TN919.3
  17. Research on Key Techniques of Frequency-Hopping Communication System,TN914.41
  18. Crossover frequency synthesizer in Research and Design,TN772
  19. Fractional- N frequency synthesizer design with adaptive frequency calibration,TN74
  20. Research on Storage Battery Feedback Diacharging of Grid-Connected Inverter,TM464
  21. Research on the Detection Methods of Wind Farm Grid Voltage Faults,TM614

CLC: > Industrial Technology > Radio electronics, telecommunications technology > Communicate > Communication theory > Phase lock, the lock-in technique
© 2012 www.DissertationTopic.Net  Mobile