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Research on AES and It’s IC Design Technique

Author: HanZuo
Tutor: QuYingJie
School: Qingdao University of Science and Technology
Course: Control Theory and Control Engineering
Keywords: AES Attack Verilog IC Design Encryption Decryption
CLC: TP309.7
Type: Master's thesis
Year: 2008
Downloads: 252
Quote: 2
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Abstract


With the social development of information industry , information security and more attention. Information security by security protocols and cryptographic algorithms , cryptographic algorithms is the foundation and core technology of information security . In addition, the current implementation of cryptographic algorithms is gradually implemented in software to achieve the transition to the hardware , the hardware implementation of cryptographic products more and more attention . Therefore, research and analysis of today's popular cryptographic algorithm and its hardware implementation of information security has great significance . AES algorithm as a new generation of U.S. Data Encryption Standard has actually become the international standard , and because of the AES algorithm is fully free and open , so the password based on the algorithm is implemented in hardware products will be more widely used . This paper first introduces the basic principles of the AES algorithm , design principles , described in detail the structure of the algorithm and its design skills for the design principles , summed up the advantages and disadvantages of the algorithm ; implementation of the algorithm . Then, the analysis of the safety performance of the AES algorithm , summarize the algorithm ability to resist the existing attacks , gives the pseudo- code of the four square attack ; latest An Algebraic attack : XSL attack . Then, in-depth analysis and research on the AES algorithm , its integrated circuit design method of encryption and decryption process are analyzed in detail , including architecture design and design of each module . Feedback operation mode and non- feedback mode, the several structure : the basic structure of loop unrolling structure, the internal pipeline structure and external pipeline structure . Finally, the authors use the Verilog HDL hardware description language design an AES encryption and decryption IP module , and a simulation test and verify , to achieve high-speed hardware encryption and decryption of AES algorithm .

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CLC: > Industrial Technology > Automation technology,computer technology > Computing technology,computer technology > General issues > Security and confidentiality > Encryption and decryption
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