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The IP Core Physical Design and Optimization of YHFT-DSP

Author: YeJing
Tutor: XingZuoCheng
School: National University of Defense Science and Technology
Course: Software Engineering
Keywords: IP core Physical design Placement and routing Reliability Verification
CLC: TP368.11
Type: Master's thesis
Year: 2007
Downloads: 67
Quote: 2
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One hand, with the continuous development of the integrated circuit (IC) design technology and manufacturing processes, market demand is increasing, complex design has become more and more designers often have to face the problem of how to be completed within the stipulated time. On the other hand, in the dual role of demand traction and technology-driven, the concept of the entire system is integrated on a single chip, the so-called on-chip system (SoC). Those area is small, fast, low power consumption, reliability, good design has the great value of the IP system will be integrated multiplexing. Whether IC design IP in SoC design, physical design is an important and difficult problem. Appears many new problems will become more complex due to the narrowing of the process parameters, such as crosstalk, electromigration problems. The physical design is the top-level system planning and the underlying modeling bridge, occupy an increasingly important position in the entire design cycle. In this paper, the chips YHFT-Dx IP based on a range of issues of concern in the physical design research, to which D3 IP has been delivered to users. The main work of this paper include: 1. Layout planning as a key step in the physical design, and its direct impact on the effect of the layout. Structural features for DSP hard-core module layout planning stage arrangement and adjustment method, as well as analysis and research in the area of ??standard cell-based layout planning, and given two IP core layout planning program. The power supply voltage drop and electromigration problem becomes very important, the power supply to each logical unit, the power grid will fill the entire chip. Therefore, power grid design is good or bad performance, power consumption, the area has a lot of impact. In the worst case, nuclear YHFT-Dx IP, combined with precise zonal power cord design technology to control the voltage drop is less than 5% of the supply voltage, and solve the serious problem of electron mobility, thus increasing the reliability of the systems sex. 3. Reduce clock skew and clock delay is the main target of the clock network planning and clock routing. Integrated manner based on balanced buffer tree clock tree clock network design process and optimization methods are described, the final results show that the global clock routing deviation control in less than 5% of the clock cycle, in line with the the clock design performance requirements. Based timing driven and congestion driven placement and routing can reduce the circuit delay to meet the timing requirements, while the number of cloth continuity issues helpful to reduce design iterations. Using Astro tools such as timing and congestion-driven physical design of YHFT-Dx IP-core, get better timing results, and also improved the design efficiency. Analysis of results indicate that the clock cycle is typical case 6ns, to achieve the design objectives. 5.IP nuclear verification is an important part of the design process is directly related to whether the IP core can be delivered. The paper design through final timing and physical verification, and provide all relevant views for SoC design.

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CLC: > Industrial Technology > Automation technology,computer technology > Computing technology,computer technology > Micro-computer > A variety of micro-computer > Microprocessor
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