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Physical Design and Optimization of Interconnection in X Stream Processor Cluster

Author: ChengYu
Tutor: ZhangMinXuan
School: National University of Defense Science and Technology
Course: Electronic Science and Technology
Keywords: Mixed insertion method Floorplan optimization Multi-level interconnection Interconnection Distribution Optimization Interconnect distribution model
CLC: TP332
Type: Master's thesis
Year: 2007
Downloads: 27
Quote: 1
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When the design process to enter the stage of the deep sub-micron, the interconnect delay in the IC has been gradually replaced gate delays become the major part of the signal delay. Interconnect the physical design and optimization have become the IC designers highly important issues of concern. Thesis, the the the X stream processor computing clusters interconnected physical design and optimization, interconnect delay optimization technology, placement and routing optimization, interconnect distribution model, carried out a detailed analysis and research. The main research and improve their work is reflected in the following aspects: First, the paper has extensively studied a variety of interconnect delay optimization technology, such as the use of better interconnect material, hierarchical interconnect structure and innovative three-dimensional integrated IC and so on. Paper also studied the method The interconnection line delay circuit optimized structure, to achieve a combination of mixed insertion method A relay insert and a low-swing circuit, and into the relay drive to optimize the long-term delay comparison result show that the mixed insertion method can more significantly reduce the long-term delay of the interconnection. Secondly, based on the semi-custom design flow, X-stream processor computing clusters layout optimization, mainly to floorplan optimization and routing optimization. Floorplan optimization work is mainly performed on the chip size and the macro cell location optimization considerations, based on the calculated within the group function module interconnection between the logical structure and data flow information to determine the relative position of the macrocell. And take full account of the macrocell placement interconnection, try to macrocells near and on the periphery of the chip, to avoid the long line across the macrocell. Through in-depth analysis of several typical interconnect distribution model, the model estimates the interconnect distribution and actual interconnection distribution of contrast, targeted to optimize the distribution of actual interconnection. The paper uses a multi-level interconnect and diagonal wiring interconnect delay optimization techniques, learn typical interconnect distribution model, combined with floorplan optimization to improve interconnect distribution based on a semi-custom design flow, thereby enhancing the overall performance of the system. Meanwhile, the placement and routing of the group, calculated based on a semi-custom process optimization design X-stream processors functional unit for the need for full-custom design shapes and sizes, and port location reference information. Finally, based on the optimized interconnect distribution, of typical interconnect distribution model slightly amended, to get closer to the X-stream processors swarm optimization calculations correction interconnect distribution model for the subsequent addition of a full-custom design functional unit of global optimize the layout to provide guidance based on. In addition, the paper also preliminary qualitative study on the application of the interconnect distribution model.

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CLC: > Industrial Technology > Automation technology,computer technology > Computing technology,computer technology > Electronic digital computer (not a continuous role in computer ) > Arithmetic unit and the controller (CPU)
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