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The Design and Implementation of High Performance Level Two Cache Controller on DSP Chip

Author: LiuSheng
Tutor: ChenShuMing
School: National University of Defense Science and Technology
Course: Electronic Science and Technology
Keywords: Cache RAM structure Lack of pipeline Write buffer Write merge Cross-border access EDMA access Data consistency
CLC: TP368.1
Type: Master's thesis
Year: 2008
Downloads: 81
Quote: 3
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The digital signal processor (DSP) to get a wide range of development and application in recent years. \The two Cache controller design is a key link in the storage structure of the two Cache RAM \How to design and implement a correct and efficient at the same time to meet the two high-frequency requirements Cache Controller is a problem worthy of study. FT-CXX our independent research and development of a high-performance fixed-point DSP, a very long instruction word (VLIW) technology within a film capable of transmitting up to eight instructions. Expected CPU frequency 600MHz, peripherals frequency of 300MHz, the two Cache (L2) of the total capacity of 1MB. The L2 controller design and implementation techniques, the main work and contributions epitomized in the following aspects: First, the analysis of the Cache design methods, a comprehensive study of the performance requirements of mainstream DSP chip Cache , design and implementation techniques, FT-CXX L2 Cache / SRAM structure, determine the L2 data body, the Tag body structure and address of the access rules, designed and implemented the L2Cache image rules, replacement algorithm, and write strategy. Secondly, for the L2 storage capacity, storage body can only support the fact that half the CPU frequency, to take measures to optimize the processing of the lack of a Cache (L1D and L1P). 1) Design a missing pipeline Ideally average of lack of consideration for each L1 only two beats; 2) design a width 64bit L1D and L2, the depth of support write merging L1D write miss buffer queue effectively reduce the waiting time of L1D write miss; 3) solutions for cross-border access issues, the program has a high efficiency, small hardware overhead and does not increase the additional burden of the compiler. Again, designed and implemented an efficient L2 SRAM the EDMA access processing mechanism. The mechanism fully tap EDMA access to the potential parallelism, using a combination of EDMA request burst (continuous hair to eight read request, write request), listener and send the data processing to streamline the number of listeners based on listener history reduced bypass and merge mechanism-based L2 data volume reduction technologies such as access, EDMA transmission efficiency greatly improve the average access a data only need 2-3 shot, and general serial passage speedup in 2.0 or more. Finally, designed and implemented an efficient data consistency maintenance mechanisms. Cache control register operations, on the other hand on the one hand to provide a write back of the listener and the data classification process. The experimental results show that the mechanism so that the overhead can be reduced more than 10% of the system typical request. In addition, the above design system to verify and logic synthesis and optimization, it SMIC 0.13 um process to meet with a Cache interface part of the operating frequency 600MHz, internal operating frequency of 300MHz requirements .

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CLC: > Industrial Technology > Automation technology,computer technology > Computing technology,computer technology > Micro-computer > A variety of micro-computer > Microprocessor
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