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Research and Implementation of Qlink-A Communicaiton Mechanism to Heterogeneous Multi-core DSP

Author: GuoBaoDong
Tutor: ChenShuMing
School: National University of Defense Science and Technology
Course: Electronic Science and Technology
Keywords: Multicore YHFT-DSP DSP Qlink link CrossBar Verification Software Simulator
CLC: TP368.1
Type: Master's thesis
Year: 2008
Downloads: 195
Quote: 1
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Multicore SoC comprehensive utilization of a multi-processor data parallel processing capabilities, as well as highly integrated SoC's ability, and is widely available in the current high-performance embedded systems. In the multi-core architecture, efficient communication mechanism is an important guarantee for high performance multi-core processors. QDSP is a heterogeneous multicore chip developed containing four YHFT-DSP/800 of the kernel and a 32-bit RISC core. A flexible hierarchical interconnect communication structure of the multi-core chip design: by CrossBar structure to achieve a 4 star DSP core interconnect chip, the the hook in CrossBar PCI-E high-speed links interconnection between with other QDSP chip chip. First, the interconnect communication structure, design-based the interconnect communication protocol of the packets Qlink support chip, chip read and write transactions, which write enable multicast transmission chip, chip read and write support for source routing and XY dimension order routing. Support the Qlink interconnect communication protocol, designed to interconnect communication interface link between the DSP core. the link interfaces flooding directors within the DSP core the EDMA nuclear CrossBar achieve chip and inter-chip bulk data transfer. The link interface of the data width is 16 bits, contains the full-duplex transmission and receiver, the transmitter and the receiver are equipped with the structure of the FIFO buffers to smooth data transfer. In order to achieve non-blocking read transaction processing in the link interface designed to a depth of 4 read transaction matching dynamic list. In order to facilitate the user the link interface design three flexible transmission control mode. Link to conduct a comprehensive in 0.13 micron smic process of the area of ??0.21mm ~ 2, frequency up to 400MHz, power consumption is about 83mW. Secondly, the communication module Qlink agreement involved the the link, CrossBar and PCI-E conducted a comprehensive functional verification. Chip interconnect testing need multiple QDSP chip cooperate with each other, used in all the RTL model will result in a very slow simulation speed pseudo DSP, and pseudo SoC model;-depth analysis of the characteristics of the communication module, designed them to customize The sequence of instructions as an incentive to enter. On the different levels of the test, the test platform built by the pseudo model efficiently interconnect communication module exhaustive testing. Again, we use the event-driven mechanism design the Qlink chip communication software simulator. The simulator is consistent with the hardware on the functional and timing, is part of QDSP software simulator can be used for performance evaluation the QDSP architecture. Finally, the analysis of the data transmission performance of the link interface. When QDSP work at 350MHz, use the link interface the nuclear between data transmission fastest speed is about 560MBps link interface for 81% of the peak bandwidth of 700MBps. When packets load a maximum of 1024 words, the data transmission overhead accounts for about 3% of the total transmission time. Based the Qlink transmission two-dimensional FFT application in the the software simulator QDSP achieve a speedup of 3.8. The link interface design to meet the demand for data transmission of the coarse-grained multi-core processors.

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CLC: > Industrial Technology > Automation technology,computer technology > Computing technology,computer technology > Micro-computer > A variety of micro-computer > Microprocessor
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