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Design and Optimization of S Unit of a 600MHz DSP Chip

Author: DaiZhaoJun
Tutor: SunYongJie
School: National University of Defense Science and Technology
Course: Electronic Science and Technology
Keywords: Digital Signal Processor DSP S arithmetic unit Shifter Full-custom design Dynamic Circuits Anti-noise capability
CLC: TP368.1
Type: Master's thesis
Year: 2008
Downloads: 39
Quote: 1
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Abstract


The digital signal processor (DSP) is a specialized microprocessor designed for processing digital signals. Since the early 1980s, the birth of the DSP technology has been developed rapidly, Currently, DSP has been widely used in various fields of social life, especially in the military, communications and control technology. DSP performance, more and more applications put forward higher requirements. FT-CXX is a research and development of high-performance 32-bit fixed-point arithmetic DSP chip, it is a very long instruction word structure within a film can be out of eight instructions at the same time, the design goal of speeds up to 600MHz, the existing domestic DSP chip the highest performance products. Of as the development of one of the officers involved in the the paragraph DSP development, responsible for the design and realization of the important components in the CPU core S part. This paper describes the optimization of the the S component design, and the full-custom made indicators reach clocked at 600MHz. S part is an important component of the FT-CXX implementation of logical, arithmetic, bit-field operations and control transfer instructions, the article describes the the S component architecture and modular division, elaborated on the S part of the logic design, logic synthesis The performance analysis, combined with the design goals developed optimization program wherein the critical path and the key member. The shifter is a major operator in the S part unit, the EXT instruction execution process needs serial shift shifter performance constraints S component design bottleneck twice, after the experiments show that only a full-custom design in order to achieve the design goals. In this paper, the dynamic circuit design of the FT-CXX shifter, and by means of full-custom layout design optimization. After the completion of the layout design shifter delay is less than 300ps, an area of ??70 × 70 μm square to reach the goal of the design is expected. Dynamic circuit performance advantages and noise margin small signal stability of the drawbacks, from the performance boost and improve noise immunity shifter design was optimized and improved by adopting omitted evaluated tube design, dual-threshold device technology and skew MOS tube technology, the circuit performance improved by more than 25%; improved noise immunity of dynamic shifter and evaluation through the analysis and discussion of the anti-noise technology for dynamic circuit noise sources, Make sure that the circuit can work within the range of permissible noise in the environment. Research projects completed full custom optimization of logic design, and a key part of the S-components, eliminating the bottleneck restricting the design performance, and laid the foundation for the completion of the S component of the overall.

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CLC: > Industrial Technology > Automation technology,computer technology > Computing technology,computer technology > Micro-computer > A variety of micro-computer > Microprocessor
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