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Design and Optimization of 600MHz Branch ALU of YHFT-DX

Author: JinCanCan
Tutor: ChenShuMing
School: National University of Defense Science and Technology
Course: Software Engineering
Keywords: DSP Features ALU Adder Shifter Full-custom design Test
CLC: TP332
Type: Master's thesis
Year: 2009
Downloads: 33
Quote: 0
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Abstract


YHFT-DX is a high-performance fixed-point DSP of the School of Computer Science, National University of Defense Technology developed an eight-outflow VLIW architecture, the CPU core frequency of 600MHz. Branch arithmetic logic unit (BALU) is an integrated the branch control function arithmetic logic member (ALU). BALU perform the operation is very complex, using a variety of complex computing limit YHFT-DX performance of key components. On the BALU the important research and engineering significance. In this paper, the BALU the full-custom design and optimization study completed the entire the BALU the circuit and layout design in 0.13um CMOS process. The simulation results show that: the BALU execution stack layout after the maximum delay of no more than 1.2ns. In the course of the study, the paper mainly do the following: 1) study of the BALU water in which the stack, the of BALU decoding stack and execution stack design goals, select the decoding stack semi-custom and full-custom implementation of the stack the design of the way. Then implemented using RTL description of the BALU the decoding stack integrated after the results show that the delay of the decoding stack 0.95ns. 2) sub-modules studied the functions of the BALU execution stack, the critical path analysis of each module, and on this basis, to limit the operation of the speed and area of ??each module of the design optimization. Solved through restructuring results elect competition of the control signal in the logic design; algorithm improvements two asymmetric decoded 40-bit shifter; increase in parallel, to optimize the critical path of the SIMD; byte by pressing processing methods, reduces the area of ??the bit operation modules. 3) adder is a very important operation unit in the processor design, The used new FCSL structure to design a 32-bit adder, and the idea of ??a limited dynamic optimization of the adder. Results show that the delay of the adder for 410PS. 4) in the layout, for complicated wiring the wiring channel layout, effectively reduces the complexity of the layout. By using this mode, the completion of the layout design of of BALU the execution stack. Factors affecting the territory reliability analysis. 5) mixed verify decoding stack RTL code and execution stack circuit extraction circuit Verilog model were completed before the simulation and post-simulation. 6) to complete a part of the circuit design of the test chip BALU, this design uses a serial scan mode, the functionality and performance of the data path of the test the BALU and register file constitutes. Pre-silicon test reached a 600MHz design goals the BALU and the data path of the register file.

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CLC: > Industrial Technology > Automation technology,computer technology > Computing technology,computer technology > Electronic digital computer (not a continuous role in computer ) > Arithmetic unit and the controller (CPU)
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