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Design and Optimization of Arithmetic and Logical Unit in 90nm Technology

Author: ChenJianMei
Tutor: XingZuoCheng；LiShaoQing
School: National University of Defense Science and Technology
Course: Software Engineering
Keywords: ALU Full-custom design Logic optimization 90nm process Pseudo-Ling sparse tree 64-bit adder
CLC: TP332
Type: Master's thesis
Year: 2009
Downloads: 35
Quote: 1
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Abstract


The integer arithmetic unit (ALU) is a high - performance microprocessor core computing member , one having a great impact on the performance of the entire microprocessor performance . In the 90 - nanometer process optimization of high - performance integer arithmetic unit design and implementation techniques to study with a wide range of application value and practical significance . Firstly X high-performance microprocessors , integer arithmetic unit conducted in-depth research and analysis . Using of mixed static timing analysis , reasonable assurance as to the timing constraints , consolidation and analysis of the performance of the various components in the consolidated results , find the critical path constraints entire computing components , and determine the need for full-custom implementation module . The paper then combined with the advantages of sparse tree and Ling algorithm , proposed an improved binary tree adder - Pseudo-Ling sparse tree , and improve the performance of the adder . For the improvement of the backward -bit tree circuit design and performance analysis , circuit simulation results show that the improved 64-bit adder delay 300ps . Finally, based on the 90 -nanometer process , improved 64-bit adder , full custom layout design , using a variety of effective measures on RC delay , crosstalk and IR Drop and other parasitic parameter effects optimized to make improvements after 64 additions the performance has been improved. Hspice simulation , full-custom design 64-bit adder logic delay of 590ps, the layout area of 100 μm × 56μm . Through the use of semi-custom design optimization and full-custom design optimization method of combining multiple levels in the algorithm , coding , logical structure , circuit layout design and optimization of the integer arithmetic unit operating frequency of 1.2GHz. Thesis research will be applied in practical engineering .

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CLC: > Industrial Technology > Automation technology,computer technology > Computing technology,computer technology > Electronic digital computer (not a continuous role in computer ) > Arithmetic unit and the controller (CPU)
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